[multi-dut] add infrastructure to update dut port to ptf port index map#2460
Merged
yxieca merged 3 commits intosonic-net:masterfrom Nov 5, 2020
Merged
[multi-dut] add infrastructure to update dut port to ptf port index map#2460yxieca merged 3 commits intosonic-net:masterfrom
yxieca merged 3 commits intosonic-net:masterfrom
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In the single DUT scenario, the DUT interface indeces exactly match with the ptf port indeces. However, in multi-dut scneario, this is not always true. Multiple DUTs are sharing the same ptf host, therefore their interface indeces need to be translated to ptf port indeces according to the topology definition. In this change, a translate map is captured from topology definition. And member method get_minigraph_facts() is added to SonicHost to help getting the minigrap facts and then update ptf port indeces. Changed test_lag_2 to use the new method to map to the correct ptf port. Signed-off-by: Ying Xie <[email protected]>
lguohan
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Nov 4, 2020
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retest vsimage please |
lguohan
approved these changes
Nov 5, 2020
Blueve
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Nov 5, 2020
kazinator-arista
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Mar 4, 2026
…e submodule head (sonic-net#12149) linkmgrd: * 05e5f4c 2022-09-20 | [Active-Active] flaky LinkmgrdBootupSequence unit tests (sonic-net#134) (HEAD -> 202205) [Jing Zhang] * 16fcadf 2022-09-13 | [active-standby] update warmboot reconciliation logic (sonic-net#129) [Jing Zhang] * e656a87 2022-09-09 | [active-active] shutdown link prober when starting as isolated (sonic-net#130) [Jing Zhang] uttilities: yinxi@ying-dev-vm-01:~/src/sonic-202205/src/sonic-utilities$ git hist github/202205..HEAD * 562188f 2022-09-14 | Use 'default' VRF when VRF name is not provided (sonic-net#2368) (HEAD -> 202205) [Sumukha Tumkur Vani] * c50ba4f 2022-09-20 | [minigraph] add option to specify golden path in load_minigraph (sonic-net#2350) [jingwenxie] * cec5ab2 2022-09-20 | [GCU]Remove GCU unique lane check for duplicate lanes platforms (sonic-net#2343) [jingwenxie] * 8d20771 2022-09-15 | Vnet_route_check Vxlan tunnel route update. (sonic-net#2281) [siqbal1986] swss: * 88371f7 2022-09-21 | [ci] Only when test stage succeeded or succeededwithissues, PR run Gcov (sonic-net#2460) (HEAD -> 202205) [Liu Shilong] * c11dbd7 2022-09-15 | [QoS] Enforce drop probability only for colors whose WRED are enabled (sonic-net#2422) [Stephen Sun] sairedis: * 80928dd 2022-09-06 | [lgtm] Add uuid library (sonic-net#1119) (HEAD -> 202205, github/202205) [Kamil Cudnik] * c147dd0 2022-09-16 | [202205][vslib]: Add SAI_PORT_ATTR_OPER_SPEED get sonic-net#1123 [Ze Gan] platform-daemon: * 9cf8adf 2022-09-21 | [ycabled] add notification for gRPC connection state transitions to IDLE/TRANSIENT_FAILURE (sonic-net#295) (HEAD -> 202205) [vdahiya12] * 1e07ae3 2022-09-20 | Use get() to fetch default value from dictionary for port admin_status sonic-net#286 [anamehra] * 157f483 2022-09-15 | [Xcvrd] Soak duplicate events and process only updated interested events (sonic-net#285) [Prince George] Signed-off-by: Ying Xie <[email protected]>
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Description of PR
Summary:
Fixes # (issue)
Type of change
Approach
What is the motivation for this PR?
In the single DUT scenario, the DUT interface indeces exactly match with the ptf port indeces. However, in multi-dut scneario, this is not always true. Multiple DUTs are sharing the same ptf host, therefore their interface indeces need to be translated to ptf port indeces according to the topology definition.
How did you do it?
In this change, a translate map is captured from topology definition. And member method get_extended_minigraph_facts() is added to SonicHost to help getting the minigrap facts and then extend it with ptf port indices with mg_facts['minigraph_ptf_indeces'].
Changed test_lag_2 to use the new method to map to the correct ptf port.
Signed-off-by: Ying Xie [email protected]
How did you verify/test it?
Tested the infrastructure with updated lag_2 test.
platform linux2 -- Python 2.7.12, pytest-4.6.5, py-1.9.0, pluggy-0.13.1
ansible: 2.8.12
rootdir: /var/src/sonic-mgmt/tests, inifile: pytest.ini
plugins: ansible-2.2.2, forked-1.3.0, xdist-1.28.0, html-1.22.1, repeat-0.8.0, metadata-1.10.0
collected 24 items
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0001-single_lag] PASSED [ 4%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0001-lacp_rate] PASSED [ 8%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0001-fallback] SKIPPED [ 12%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0003-single_lag] PASSED [ 16%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0003-lacp_rate] PASSED [ 20%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0003-fallback] SKIPPED [ 25%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0002-single_lag] PASSED [ 29%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0002-lacp_rate] PASSED [ 33%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0002-fallback] SKIPPED [ 37%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0004-single_lag] PASSED [ 41%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0004-lacp_rate] PASSED [ 45%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-06|PortChannel0004-fallback] SKIPPED [ 50%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0001-single_lag] PASSED [ 54%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0001-lacp_rate] PASSED [ 58%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0001-fallback] SKIPPED [ 62%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0003-single_lag] PASSED [ 66%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0003-lacp_rate] PASSED [ 70%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0003-fallback] SKIPPED [ 75%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0002-single_lag] PASSED [ 79%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0002-lacp_rate] PASSED [ 83%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0002-fallback] SKIPPED [ 87%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0004-single_lag] PASSED [ 91%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0004-lacp_rate] PASSED [ 95%]
pc/test_lag_2.py::test_lag[str2-7050cx3-acs-07|PortChannel0004-fallback] SKIPPED [100%]
------------------------------------------------------------------------ generated xml file: /tmp/logs-01/tr.xml -------------------------------------------------------------------------