Allow multiple devices in one design and add device configuration op (`aiex.configure`) by andrej · Pull Request #2532 · Xilinx/mlir-aie

andrej · 2025-08-22T21:23:47Z

allow devices to have symbol names and add compile-time flags to decide which devices/sequences should be compiled
for files that are specific to a certain device, aiecc.py will generate separate files for each device
during core ELF generation, write paths back to MLIR instead of relying on a fixed path in aiecc.py; to this end, add a "set elf for core" pass
factor out some of the address generation for write32/blockwrites that was duplicated code (will also be reused in future reconfig PR)
make AIECreatePathFindFlows work in multi-threaded environment with multiple devices
factor out getOrCreateDataMemref (with deduplication) into a utility function (this will become useful for future reconfig PR)
add a aiex.configure op which for now has no lowering yet (this will be useful for future PRs)

Examples of new syntax:

good
bad

andrej · 2025-08-27T21:17:02Z

Looks like tests finally pass. After review, I'll squash the commits before merging and get rid of the meaningless commit messages.

fifield

I get some failures when running with Vitis.

A number of them are like this:

********************
FAIL: AIE_TEST :: unit_tests/aie/05_tiledma/aie.mlir (15 of 189)
******************** TEST 'AIE_TEST :: unit_tests/aie/05_tiledma/aie.mlir' FAILED ********************
Exit Code: 1

Command Output (stdout):
--
error: input MLIR must contain at least one aie.device

This one manually uses elf_file attribute and failed:

/work/acdc/build/aie/test/unit_tests/chess_compiler_tests_aie2/02_precompiled_kernel/aie.mlir.prj/input_with_addresses.mlir:9:17: error: 'aie.core' op When `elf_file` attribute is specified, core body must be empty (consist of exactly one `aie.end` op).
    %core_1_3 = aie.core(%tile_1_3) {

fifield · 2025-08-28T15:58:16Z

include/aie/Dialect/AIE/IR/AIEOps.td

+    If the `elf_file` attribute is present, no MLIR besides a terminator may be
+    present in the core; in that case, the binary file linked dictates what 
+    will run in the core. The path specified should is relative to the MLIR
+    file.


Why does the presence of the attribute require that the core body is deleted? It seems to hard code things for the current aiecc use case.

I thought it would be more clear this way, removing the ambiguity of which code gets executed if both the attribute is there and there is code inside the body. If this complicates some use case I'm not aware of, I can remove this restriction.

I have left this check in place for now. Let me know if you want to discuss it further.

fifield · 2025-09-02T20:54:02Z

python/compiler/aiecc/main.py

+        if (opts.cdo or opts.xcl or opts.pdi) and opts.execute:
+            await self.process_cdo(input_physical_with_elfs_str, device_name)
+
+        processes = []


This erases the process.append of line 1519, resulting in:

/work/vitis-venv/bin/python3.12 /work/acdc/build/aie/bin/aiecc.py --aiesim --xchesscc --xbridge --no-compile-host /work/acdc/aie/test/unit_tests/chess_compiler_tests_aie2/03_simple/aie.mlir -I/work/acdc/build/aie/runtime_lib/x86_64/test_lib/include -L/work/acdc/build/aie/runtime_lib/x86_64/test_lib/lib -ltest_lib /work/acdc/aie/test/unit_tests/chess_compiler_tests_aie2/03_simple/test.cpp /work/acdc/build/aie/python/aie/compiler/aiecc/main.py:1528: RuntimeWarning: coroutine 'FlowRunner.gen_sim' was never awaited

andrej · 2025-09-02T21:21:55Z

I get some failures when running with Vitis.

Oh, that's not good. Looks like none of the tests in unit_tests/aie ran, I didn't realize this. I'll run those manually.

Would it be fine to refactor those to require the code be wrapped in an aie.device? That would make things easier on my end, but if for backwards-compatibility we need to support tiles etc directly under module, I can make that possible too.

fifield · 2025-09-02T23:08:39Z

I get some failures when running with Vitis.

Oh, that's not good. Looks like none of the tests in unit_tests/aie ran, I didn't realize this. I'll run those manually.

Would it be fine to refactor those to require the code be wrapped in an aie.device? That would make things easier on my end, but if for backwards-compatibility we need to support tiles etc directly under module, I can make that possible too.

The current state of things was a convenience for backward compatibility. IIRC VC1902 is assumed if aie.device is missing. In my opinion we can refactor the older tests to include aie.device and remove the backward compatibility feature.

AndraBisca · 2025-09-03T14:21:00Z

include/aie/Dialect/AIEX/IR/AIEX.td

+  let hasVerifier = 1;
+}
+
+def AIE_RunOp: AIEX_Op<"run", [HasParent<"ConfigureOp">]> {


Could you please add a short summary for this operation?

AndraBisca · 2025-09-03T14:34:25Z

lib/Dialect/AIE/Transforms/AIECreatePathFindFlows.cpp

                  ConversionPatternRewriter &rewriter) const override {
    Operation *Op = flowOp.getOperation();
+    DeviceOp d = flowOp->getParentOfType<DeviceOp>();
+    assert(d);


Does this assert check if a device was found? Since asserts can be disabled in certain compilation modes it might be better to use an if statement.

Indeed, replaced the assert with a proper error.

AndraBisca · 2025-09-03T14:48:10Z

lib/Targets/AIETargetLdScript.cpp

  DenseMap<TileID, Operation *> tiles;
  DenseMap<Operation *, SmallVector<BufferOp, 4>> buffers;

+  DeviceOp targetOp = AIE::DeviceOp::getForSymbolInModule(module, deviceName);


Does this need a check?

It does. Added

fifield · 2025-09-23T19:32:23Z

lib/Dialect/AIEX/Transforms/AIEDmaToNpu.cpp

-      global = rewriter.create<memref::GlobalOp>(
-          op->getLoc(), name, rewriter.getStringAttr("private"), memrefType,
-          initVal, true, nullptr);
+      global = getOrCreateDataMemref(rewriter, dev, op.getLoc(), words);


I implemented the optimization you've refactored here, but I had been wondering if it should be removed instead. The reason is that I had to disable it for some cases in a downstream branch because unlike the current scheme, some runtime schemes patch the address in the data before writing it to the shim dma (e.g. cert, maybe "new elf" too). So the data can't be shared in those cases.

I just factored it out because I ended up using it multiple places and didn't want to have code duplication. Hopefully that should make removing it (or somehow adapting it to the cert case) easier down the line too.

…rings

… in file

andrej · 2025-09-24T23:38:09Z

I think this PR is ready for re-review @fifield @AndraBisca @jgmelber

Changes since the last round:

Fixed some older AIE1 tests that aren't ran by the CI. Some tests still fail, but these also seem to fail on main. I attached the list of tests that fail for me on main below for future reference. I'm re-running the whole test suite right now, and hopefully the set of tests that fail will be the same on this branch as on main. I'll report back and get to fixing them if not.
When no device is specified for compilation, passes that require a device to be selected now choose the one named "main" and issue an error if there is no such device, instead of picking the first device in the file. Note that "main" is the default name, so unnamed devices are implicitly named "main".
Made device selectable for transaction sequence and control packet passes; before, these would lower all devices and error if one of the devices was not lowerable. Changed Jeff's add_one_two example to combine aie1.mlir and aie2.mlir files to test this multiple-device scenario.
Removed "set ELF for core" pass; replaced with processing in Python
Fixed some checks and other details pointed out during reviews.
git diff --name-only main | grep -E "\.(h|hpp|c|cpp|cc)" | xargs clang-format-17 -i

Note: CI failed during setup for building the wheels, trying to install the qemu package. I'll try restarting it, this seems unrelated to the PR.

Tests that failed/didn't run on main

********************
Unsupported Tests (219):
  AIE_TEST :: Integration/Dialect/AIEVec/64x32x64xbf16_4x8x4_packed_gemm/gemm-64x32x64-bf16.mlir
  AIE_TEST :: Integration/Dialect/AIEVec/i16xi16_gemm/gemm64_int16.mlir
  AIE_TEST :: Integration/Dialect/AIEVec/i32xi32_gemm/gemm64_int32.mlir
  AIE_TEST :: Integration/Dialect/AIEVec/ml_unaligned_read/i16/kernel.mlir
  AIE_TEST :: Integration/Dialect/AIEVec/ml_unaligned_read/i32/kernel.mlir
  AIE_TEST :: Integration/Dialect/AIEVec/ml_unaligned_read/i8/kernel.mlir
  AIE_TEST :: Integration/Dialect/AIEVec/v1_unaligned_read/i16/kernel.mlir
  AIE_TEST :: Integration/Dialect/AIEVec/v1_unaligned_read/i32/kernel.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_abs_v16/bf16_abs.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_abs_v32/bf16_abs.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_cast_float/bf16_cast_float.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_ceil_v16/bf16_ceil.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_ceil_v32/bf16_ceil.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_erf_v16/bf16_erf.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_erf_v32/bf16_erf.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_floor_v16/bf16_floor.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_floor_v32/bf16_floor.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_neg/bf16_neg.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_sigmoid_v16bf16/bf16_sigmoid.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_sigmoid_v32bf16/bf16_sigmoid.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16_tanh/bf16_tanh.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_add_elem/bf16xbf16_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_mul_elem/bf16xbf16_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1/bf16xbf16_mul_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1/bf16xbf16_mul_elem_2d_broadcast_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1024/bf16xbf16_mul_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1024/bf16xbf16_mul_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_mul_elem_16x1024_broadcast_1024/bf16xbf16_mul_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sel/bf16xbf16_sel.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem/bf16xbf16_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem_16x1024_broadcast_1/bf16xbf16_sub_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem_16x1024_broadcast_1/bf16xbf16_sub_elem_2d_broadcast_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem_16x1024_broadcast_1024/bf16xbf16_sub_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem_16x1024_broadcast_1024/bf16xbf16_sub_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem_16x1024_broadcast_1024/bf16xbf16_sub_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem_dyn_size/bf16xbf16_sub_elem_dyn_size.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xbf16_sub_elem_dyn_size_2d/bf16xbf16_sub_elem_dyn_size_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xfloat_add_elem/bf16xfloat_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xfloat_add_elem/floatxbf16_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xfloat_sub_elem/bf16xfloat_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bf16xfloat_sub_elem/floatxbf16_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/bfloat16_cast.mlir
  AIE_TEST :: Integration/Dialect/TOSA/float_abs_v16/float_abs.mlir
  AIE_TEST :: Integration/Dialect/TOSA/float_cast.mlir
  AIE_TEST :: Integration/Dialect/TOSA/float_cast_bf16/float_cast_bf16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/float_neg/float_neg.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_add_elem/floatxfloat_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_sel/floatxfloat_sel.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_sub_elem/floatxfloat_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_sub_elem_16x1024_broadcast_1/floatxfloat_sub_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_sub_elem_16x1024_broadcast_1/floatxfloat_sub_elem_2d_broadcast_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_sub_elem_16x1024_broadcast_1024/floatxfloat_sub_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_sub_elem_16x1024_broadcast_1024/floatxfloat_sub_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/floatxfloat_sub_elem_16x1024_broadcast_1024/floatxfloat_sub_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_abs_v32/i16_abs.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_arithmetic_right_shift/i16_arithmetic_right_shift.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_bitwise_and/i16_bitwise_and.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_bitwise_not/i16_bitwise_not.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_bitwise_or/i16_bitwise_or.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_bitwise_xor/i16_bitwise_xor.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_cast.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_cast_i32/i16_cast_i32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_cast_i8/i16_cast_i8.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16_neg/i16_neg.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_add_elem/i16xi16_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_mul_elem/i16xi16_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1/i16xi16_mul_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1/i16xi16_mul_elem_2d_broadcast_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1024/i16xi16_mul_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1024/i16xi16_mul_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_mul_elem_16x1024_broadcast_1024/i16xi16_mul_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_mul_elem_i32/i16xi16_mul_elem_i32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_sel/i16xi16_sel.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_sub_elem/i16xi16_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_sub_elem_16x1024_broadcast_1/i16xi16_sub_elem_2d_broadcast_1d_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_sub_elem_16x1024_broadcast_1/i16xi16_sub_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_sub_elem_16x1024_broadcast_1024/i16xi16_sub_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_sub_elem_16x1024_broadcast_1024/i16xi16_sub_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi16_sub_elem_16x1024_broadcast_1024/i16xi16_sub_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_add_elem_v16/i16xi32_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_add_elem_v16/i32xi16_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_add_elem_v32/i16xi32_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_mul_elem/i16xi32_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_mul_elem/i32xi16_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_sub_elem_v16/i16xi32_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_sub_elem_v16/i32xi16_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i16xi32_sub_elem_v32/i16xi32_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_abs_v16/i32_abs.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_arithmetic_right_shift/i32_arithmetic_right_shift.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_bitwise_and/i32_bitwise_and.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_bitwise_not/i32_bitwise_not.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_bitwise_or/i32_bitwise_or.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_bitwise_xor/i32_bitwise_xor.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_cast.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_cast_i16/i32_cast_i16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_cast_i8/i32_cast_i8.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32_neg/i32_neg.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_add_elem/i32xi32_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_mul_elem/i32xi32_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1/i32xi32_mul_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1/i32xi32_mul_elem_2d_broadcast_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1024/i32xi32_mul_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1024/i32xi32_mul_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_mul_elem_16x1024_broadcast_1024/i32xi32_mul_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sel/i32xi32_sel.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem/i32xi32_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1/i32xi32_sub_elem_2d_broadcast_1d_unit_dim_v16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1/i32xi32_sub_elem_2d_broadcast_1d_unit_dim_v32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1/i32xi32_sub_elem_2d_broadcast_scalar_v16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1/i32xi32_sub_elem_2d_broadcast_scalar_v32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_1d_reshape_v16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_1d_reshape_v32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_1d_v16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_1d_v32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_2d_v16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i32xi32_sub_elem_16x1024_broadcast_1024/i32xi32_sub_elem_2d_broadcast_2d_v32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_abs_v64/i8_abs.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_arithmetic_right_shift/i8_arithmetic_right_shift.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_bitwise_and/i8_bitwise_and.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_bitwise_not/i8_bitwise_not.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_bitwise_or/i8_bitwise_or.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_bitwise_xor/i8_bitwise_xor.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_cast.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_cast_i16/i8_cast_i16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_cast_i32/i8_cast_i32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8_neg/i8_neg.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi16_add_elem/i16xi8_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi16_add_elem/i8xi16_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi16_mul_elem_v16/i8xi16_mul_elem_v16.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi16_mul_elem_v32/i16xi8_mul_elem_v32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi16_mul_elem_v32/i8xi16_mul_elem_v32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi16_sub_elem/i16xi8_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi16_sub_elem/i8xi16_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi32_add_elem/i32xi8_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi32_add_elem/i8xi32_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi32_mul_elem/i32xi8_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi32_mul_elem/i8xi32_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi32_sub_elem/i32xi8_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi32_sub_elem/i8xi32_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_add_elem/i8xi8_add_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_mul_elem/i8xi8_mul_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_mul_elem_16x1024_broadcast_1/i8xi8_mul_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_mul_elem_16x1024_broadcast_1/i8xi8_mul_elem_2d_broadcast_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_mul_elem_16x1024_broadcast_1024/i8xi8_mul_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_mul_elem_16x1024_broadcast_1024/i8xi8_mul_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_mul_elem_16x1024_broadcast_1024/i8xi8_mul_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_mul_elem_i32/i8xi8_mul_elem_i32.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_sel/i8xi8_sel.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_sub_elem/i8xi8_sub_elem.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_sub_elem_16x1024_broadcast_1/i8xi8_sub_elem_2d_broadcast_1d_scalar.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_sub_elem_16x1024_broadcast_1/i8xi8_sub_elem_2d_broadcast_1d_unit_dim.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_sub_elem_16x1024_broadcast_1024/i8xi8_sub_elem_2d_broadcast_1d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_sub_elem_16x1024_broadcast_1024/i8xi8_sub_elem_2d_broadcast_1d_reshape.mlir
  AIE_TEST :: Integration/Dialect/TOSA/i8xi8_sub_elem_16x1024_broadcast_1024/i8xi8_sub_elem_2d_broadcast_2d.mlir
  AIE_TEST :: Integration/Dialect/TOSA/ui8_cast.mlir
  AIE_TEST :: Integration/julia_by_lines/aie.mlir
  AIE_TEST :: Targets/AIEGenerateXAIE/test_herd_xaie0.mlir
  AIE_TEST :: Targets/AIETargetAirbin/aie.mlir
  AIE_TEST :: create-cores/test_dma2.mlir
  AIE_TEST :: create-cores/test_dma3.mlir
  AIE_TEST :: create-flows/maxiter_err_test.mlir
  AIE_TEST :: create-locks/test_lock7.mlir
  AIE_TEST :: create-locks/test_lock_shimdma.mlir
  AIE_TEST :: create-packet-flows/test_create_packet_flows6.mlir
  AIE_TEST :: create-packet-flows/test_pktflow_weight_pusher.mlir
  AIE_TEST :: herd-routing/test_herd_routing0.mlir
  AIE_TEST :: herd-routing/test_herd_routing1.mlir
  AIE_TEST :: herd-routing/test_herd_routing2.mlir
  AIE_TEST :: merge-buffers/test_buffer_merge0.mlir
  AIE_TEST :: npu-xrt/add_one_ctrl_packet_col_overlay/run.lit
  AIE_TEST :: npu-xrt/add_one_objFifo/test.py
  AIE_TEST :: npu-xrt/add_one_objFifo_elf/test.py
  AIE_TEST :: npu-xrt/adjacent_memtile_allocation/onelargefifo_on_2memtile/ext_to_core_L2_placed.py
  AIE_TEST :: npu-xrt/adjacent_memtile_allocation/onelargefifo_on_3memtile/ext_to_core_L2_placed.py
  AIE_TEST :: npu-xrt/adjacent_memtile_allocation/twofifo_one_2memtile/ext_to_core_L2_placed.py
  AIE_TEST :: npu-xrt/cascade_flows/run.lit
  AIE_TEST :: npu-xrt/device_width/aie2.py
  AIE_TEST :: npu-xrt/dma_complex_dims/aie2.py
  AIE_TEST :: npu-xrt/dma_task_large_linear/aie2.py
  AIE_TEST :: npu-xrt/dynamic_object_fifo/nested_loops/aie2.py
  AIE_TEST :: npu-xrt/dynamic_object_fifo/ping_pong/aie2.py
  AIE_TEST :: npu-xrt/dynamic_object_fifo/reduction/aie2.py
  AIE_TEST :: npu-xrt/dynamic_object_fifo/sliding_window/aie2.py
  AIE_TEST :: npu-xrt/dynamic_object_fifo/two_core_sliding_window/aie2.py
  AIE_TEST :: npu-xrt/matrix_multiplication_using_cascade/run.lit
  AIE_TEST :: npu-xrt/matrix_transpose/aie2.py
  AIE_TEST :: npu-xrt/memtile_dmas/blockwrite_using_locks/run.lit
  AIE_TEST :: npu-xrt/memtile_dmas/writebd/run.lit
  AIE_TEST :: npu-xrt/memtile_dmas/writebd_tokens/run.lit
  AIE_TEST :: npu-xrt/objectfifo_repeat/compute_repeat/aie2.py
  AIE_TEST :: npu-xrt/objectfifo_repeat/distribute_repeat/aie2.py
  AIE_TEST :: npu-xrt/objectfifo_repeat/init_values_repeat/aie2.py
  AIE_TEST :: npu-xrt/objectfifo_repeat/simple_repeat/aie2.py
  AIE_TEST :: npu-xrt/runtime_cumsum/run.lit
  AIE_TEST :: npu-xrt/tile_mapped_read/run.lit
  AIE_TEST :: npu-xrt/two_col/run.lit
  AIE_TEST :: npu-xrt/vec_vec_add_objfifo_init/aie2.py
  AIE_TEST :: npu-xrt/vector_scalar_using_dma/run.lit
  AIE_TEST :: python/python_passes.py
  AIE_TEST :: unit_tests/aie/12_julia/aie.mlir
  AIE_TEST :: unit_tests/aie/13_julia_fp/aie.mlir
  AIE_TEST :: unit_tests/aie/27_single_L1_single_lock/aie2.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/bf16_exp_lut/bf16_exp_lut-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/bf16_max_reduce/bf16_max_reduce-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/bf16xbf16_mul_elem/bf16xbf16_mul_elem-llvm-scalar.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/bf16xbf16_mul_elem/bf16xbf16_mul_elem-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/bf16xbf16_mul_elem_2/bf16xbf16_mul_elem-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/floatxfloat_mul_elem/floatxfloat_mul_elem-llvm-scalar.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/floatxfloat_mul_elem/floatxfloat_mul_elem-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i16xi16_mul_elem/i16xi16_mul_elem-llvm-scalar.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i16xi16_mul_elem/i16xi16_mul_elem-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i16xi16_mul_elem_2/i16xi16_mul_elem-llvm-scalar.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i16xi16_mul_elem_2/i16xi16_mul_elem-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i32xi32_mul_elem/i32xi32_mul_elem-llvm-scalar.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i32xi32_mul_elem/i32xi32_mul_elem-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i8xi8_mul_elem/i8xi8_mul_elem-llvm-scalar.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i8xi8_mul_elem/i8xi8_mul_elem-llvm.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i8xi8_mul_elem_2/i8xi8_mul_elem-llvm-scalar.mlir
  AIE_TEST :: unit_tests/aievec_tests/aie2/i8xi8_mul_elem_2/i8xi8_mul_elem-llvm.mlir

mawad-amd · 2025-09-25T00:29:04Z

(Sorry, I updated the branch by mistake; too many CIs are failing and I had this PR open to check which CIs are failing across PRs).

andrej · 2025-09-25T16:29:21Z

Can now definitely confirm that after local testing, the exact same tests fail as on main, so we should be good on that front. Don't know what's up with all the CI failures but I think they were intermittent.

Waiting on #2612 to get merged because this conflicted with that, then we should be good.

fifield · 2025-09-25T18:14:21Z

include/aie/Dialect/AIE/Transforms/AIEPasses.h

 std::unique_ptr<mlir::OperationPass<DeviceOp>>
 createAIEGenerateColumnControlOverlayPass();
 std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIEAssignTileCtrlIDsPass();
+std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIESetELFforCorePass();


Suggested change

std::unique_ptr<mlir::OperationPass<DeviceOp>> createAIESetELFforCorePass();

I think this was removed?

Removed, thanks for catching this

fifield · 2025-09-25T18:14:40Z

include/aie/Dialect/AIEX/IR/AIEXDialect.h

+#include "mlir/IR/BuiltinAttributes.h"
+
+namespace xilinx::AIEX {
+const char defaultRuntimeSequenceName[] = "sequence";


Could this be in the op like RuntimeSequenceOp::defaultName and still work in tablegen?
Or better,

let extraClassDeclaration = [{ llvm::StringRef getDefaultName() { return "sequence"; } }];

I think I can do it but it would have to be a static method, since the getDefaultRuntimeSequenceName() gets called when the builder is instantiated but before the Op gets created.

fifield · 2025-09-25T18:14:57Z

lib/Conversion/AIEToConfiguration/AIEToConfiguration.cpp

                                 AIEDevice::npu1_3col, AIEDevice::npu1};
-  auto device = builder.create<DeviceOp>(loc, devices[columns - 1]);
+  auto device = builder.create<DeviceOp>(
+      loc, devices[columns - 1], StringAttr::get(builder.getContext(), "main"));


Is the intent to use the default name here? I know the getDefaultName() doesn't exist, but maybe like,

Suggested change

loc, devices[columns - 1], StringAttr::get(builder.getContext(), "main"));

loc, devices[columns - 1], StringAttr::get(builder.getContext(), DeviceOp::getDefaultName()));

Or have a constructor that fills in the default,

Suggested change

loc, devices[columns - 1], StringAttr::get(builder.getContext(), "main"));

loc, devices[columns - 1]);

lib/Dialect/AIE/Transforms/AIECanonicalizeDevice.cpp

lib/Dialect/AIEX/IR/AIEXDialect.cpp

fifield · 2025-09-25T18:37:03Z

python/compiler/aiecc/cl_arguments.py

+    parser.add_argument(
+        "--ctrlpkt-dma-seq-name",
+        dest="ctrlpkt_dma_seq_name",
+        default="{0}_ctrlpkt_dma_seq.bin",
+        help="Output filename for control packet DMA sequence. `{0}` is replaced with the device name.",


This will get deleted with #2407

Looking forward to #2407, seems much cleaner for control packet lowering

fifield · 2025-09-25T18:38:15Z

test/dialect/AIEX/sequence_with_configures_bad.mlir

@@ -0,0 +1,82 @@
+//===- sequence_with_configures.mlir ---------------------------*- MLIR -*-===//


Suggested change

//===- sequence_with_configures.mlir ---------------------------*- MLIR -*-===//

//===- sequence_with_configures_bad.mlir -----------------------*- MLIR -*-===//

fifield · 2025-09-25T18:39:41Z

test/npu-xrt/add_one_two/aie.mlir

I have more of this test merging in:
2e5cdc1
249dc07
5a4672d

discussed that it's fine to leave this one merged in this PR

fifield · 2025-09-25T18:42:12Z

third_party/bootgen

Is the change to bootgen intended?

no, thanks for catching

fifield · 2025-09-25T18:42:56Z

utils/build-llvm.sh

I think the changes to this file are unrelated.

indeed, thanks for catching

andrej · 2025-09-30T20:20:59Z

Since the JIT cache issues (#2621) that are causing some intermittent CI test failures here are orthogonal to the content of this PR, as agreed with @fifield I'm merging this.

…(`aiex.configure`) (Xilinx#2532)

Allow multiple devices with names; refactorings

a61bdd1

andrej force-pushed the reconfig-clean branch from 0150248 to a61bdd1 Compare August 22, 2025 21:24

andrej changed the title ~~Allow multiple devices in one design~~ Allow multiple devices in one design and add device configuration op (aiex.configure) Aug 22, 2025

andrej added 14 commits August 22, 2025 15:45

fixes 1

415dd91

fixes 2

5ef4d24

fixes 3

ddf1615

change to region-based syntax and add some tests

22cfe40

fixes 4

6c1f28c

fixes 5

22f76f5

fix one million

b5ab950

oops

473bbef

fix one million and one

deb46ee

Merge branch 'main' into reconfig-clean

6d261d1

fix one million and two

3aca900

fixes one million and three

aa9ccdb

fix one million and five

e85e889

that was dumb

102a00e

andrej marked this pull request as ready for review August 27, 2025 21:16

andrej requested review from AndraBisca, fifield and stephenneuendorffer as code owners August 27, 2025 21:16

fifield mentioned this pull request Aug 28, 2025

Core file path set to tmpdirname #2544

Merged

fifield reviewed Sep 2, 2025

View reviewed changes

AndraBisca reviewed Sep 3, 2025

View reviewed changes

clang-format/black

19dd016

fifield mentioned this pull request Sep 22, 2025

Reduce non-determinism in router #2603

Merged

replace set-elf-for-core pass with code in aiecc.py main

551b043

fifield reviewed Sep 23, 2025

View reviewed changes

andrej added 6 commits September 23, 2025 14:33

make which device to compile configurable for AIEToConfiguration lowe…

272ead7

…rings

refactor add_one_two test to use multiple devices in same file

e016165

make 'main' the default device, instead of picking first device found…

71df8a1

… in file

address Andra's comments

52dc724

clang-format/black

0088ed6

clang-format seventeen

9063ade

fifield reviewed Sep 25, 2025

View reviewed changes

jgmelber mentioned this pull request Sep 25, 2025

Support for multiple devices in a module #2443

Closed

jgmelber added this to the IRON Release 1.2.0 milestone Sep 25, 2025

jgmelber assigned andrej Sep 25, 2025

andrej added 2 commits September 25, 2025 16:30

Merge branch 'main' into reconfig-clean

dd1e206

address Jeff's comments

ec9add7

andrej force-pushed the reconfig-clean branch from 2ef466d to ec9add7 Compare September 26, 2025 21:10

andrej added 3 commits September 26, 2025 15:10

Merge branch 'main' into reconfig-clean

988fd88

clang format

deff8c3

make sure tests regenerate JIT cache

08f611d

andrej mentioned this pull request Sep 30, 2025

Make sure CI tests do not use previous run's JIT cache #2620

Closed

andrej added this pull request to the merge queue Sep 30, 2025

Merged via the queue into Xilinx:main with commit e62aad0 Sep 30, 2025
53 checks passed

andrej deleted the reconfig-clean branch September 30, 2025 20:43

fifield pushed a commit to fifield/mlir-aie that referenced this pull request Nov 12, 2025

Allow multiple devices in one design and add device configuration op …

06f5e98

…(`aiex.configure`) (Xilinx#2532)

	loc, devices[columns - 1], StringAttr::get(builder.getContext(), "main"));
	loc, devices[columns - 1], StringAttr::get(builder.getContext(), DeviceOp::getDefaultName()));

	loc, devices[columns - 1], StringAttr::get(builder.getContext(), "main"));
	loc, devices[columns - 1]);

		@@ -0,0 +1,82 @@
		//===- sequence_with_configures.mlir ---------------------------- MLIR --===//

	//===- sequence_with_configures.mlir ---------------------------- MLIR --===//
	//===- sequence_with_configures_bad.mlir ------------------------ MLIR --===//

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