Fixes to minigraph generation for linecards in a VoQ Chassis

[sanmalho-git]

Description of PR

Summary:
Fixes # (issue)

Type of change

• Bug fix
• Testbed and Framework(new/improvement)
• Test case(new/improvement)

Back port request

• 201911

Approach

What is the motivation for this PR?

PR# 4479 added support for minigraph generation for packet based chassis.

However, this broke the generated minigraph for linecards in a VoQ chassis.

There were two issues in the minigraph generated with this PR:

• In Cpg
  • Missing BGPRouterDeclaration section for remote asics - <remote_linecard>-ASIC<#>
  • For multi-asic linecard, missing BGPRouterDeclaraion section for my asics - ASIC<#>
• In Dpg, we are missing the DeviceDataPlaneInfo for my asics in a multi-asic linecard
  • This is generated in template_dpg_asic, which is dependent on asic_topo_config.
    For voq_chassis, asic_topo_config is empty dictionary - as the iBGP connections depend on the what linecards are present in the chassis, and also what asics are on each linecard.

How did you do it?

To fix the above issues:

• create an almost empty asic topology file for our multi-asic linecard with slot0.
• In config_sonic_basedon_testbed.yml, when dealing with voq switch_type, before running through the Jinja2 templates,
  change slot0 in the asic_topo_config to the slot_num that is defined in the inventory.

Below is the asic topology for a multi-asic linecard Nokia_IXR7250e_36x400G card (in vars/topo_Nokia_IXR7250e_36x400G.yml) that is added:

slot0:
    ASIC0:
      topology:
        NEIGH_ASIC:
      configuration_properties:
        common:
          asic_type: FrontEnd
      configuration:

    ASIC1:
      topology:
        NEIGH_ASIC:
      configuration_properties:
        common:
          asic_type: FrontEnd
      configuration:

How did you verify/test it?

Generated minigraph for single and multi-asic linecards in a VoQ chassis and validated with:

• loading minigraph on the linecards
• Running iface_naming mode and test_interfaces on the linecards that exercise minigraph_facts on host and asic level.

Any platform specific information?

Supported testbed topology if it's a new test case?

Documentation

[abdosi]

why this is removed ?

[sanmalho-git]

Now that we asic_topo_config defined for multi-asic line cards, this is covered by iterating over asic_topo_config at line 203.

[abdosi]

what is need of this change ?

[sanmalho-git]

Two reasons:

• For multi-asic, the asic DeviceDataPlanInfo defines port channels with 1 leading 0 (like PortChannel02), while the host level DeviceDataPlanInfo defines the port channels with 3 leading 0's (like PortChannel0002). So, this mismatch causes some tests to fail. Example:
  • iface_namingmode/test_iface_namingmode.py::TestShowInterfaces::test_show_interfaces_portchannel. In this test we get minigraph_facts for duthost with would be padded with 3 0's and check against 'show interfaces portchannel' which from the asic config_db.json generated from minigraph would be padded to only 1 0.
• If we have a combination of single asic and multi-asic linecards, then in show commands on single asic we would have port channels padded with 3 0's, while on multi-asic they would be padded with only 1 0. So, did the change to have consistency across single and multi-asic line cards

[abdosi]

@sanmalho-git i think you might not have this change #4576.
After above PR External Portchannel will always have 4 digit. Can you revert this particular change and then we can merge the PR. I have verified other change is good.

[sanmalho-git]

Yes - I missed that PR in my testing. I have reverted the commit that changed the PortChannels to have 2 digits instead of 4.