[Accton/AS4630] update reg use for new CPLD FW#8115
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seanwu-ec wants to merge 3 commits intosonic-net:masterfrom
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[Accton/AS4630] update reg use for new CPLD FW#8115seanwu-ec wants to merge 3 commits intosonic-net:masterfrom
seanwu-ec wants to merge 3 commits intosonic-net:masterfrom
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1. Update CPLD reg use: fan_dir, LEDs(POE, DIAG, PSU1/2, FAN) and
PSU power_good
2. Improve the PSU model/serial_num reading to avoid illegal char.
3. Correct typos in cpld.c
Signed-off-by: Sean Wu <sean_wu@edge-core.com>
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/azpw run |
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/AzurePipelines run |
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Azure Pipelines successfully started running 1 pipeline(s). |
Contributor
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Please merge #5389 before this PR. I will fix the conflict then. Thanks. |
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can you resolve conflict? |
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Done. Thanks |
* Correct tx_disable reg bit polarity. Signed-off-by: Sean Wu <sean_wu@edge-core.com>
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/azpw run Azure.sonic-buildimage |
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/AzurePipelines run Azure.sonic-buildimage |
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Azure Pipelines successfully started running 1 pipeline(s). |
5 tasks
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The code was fixed by PR8450 & PR9744. |
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Models : AS4630-54PE, AS4630-54TE
PSU power_good
Improve the PSU model/serial_num reading to avoid illegal char.Done by PR#5389Signed-off-by: Sean Wu sean_wu@edge-core.com
Why I did it
Change registers use according to the newly released CPLD FW spec.
How I did it
Change registers use according to the newly released CPLD FW spec.
How to verify it
show platform psustatus, check if there are no illegal characters within.Which release branch to backport (provide reason below if selected)
Description for the changelog
[Accton/AS4630] update reg use for new CPLD FW
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