Skip to content

fix: Ensure that destination register is allocated when moving between registers in brillig gen #4316

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
TomAFrench merged 1 commit into from
Feb 9, 2024
Merged

fix: Ensure that destination register is allocated when moving between registers in brillig gen #4316

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
5 changes: 4 additions & 1 deletion compiler/noirc_evaluator/src/brillig/brillig_ir.rs
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -916,8 +916,11 @@ impl BrilligContext {
//
// This means that the arguments will be in the first `n` registers after
// the number of reserved registers.
let (sources, destinations) =
let (sources, destinations): (Vec<_>, Vec<_>) =
arguments.iter().enumerate().map(|(i, argument)| (*argument, self.register(i))).unzip();
destinations
.iter()
.for_each(|destination| self.registers.ensure_register_is_allocated(*destination));
self.mov_registers_to_registers_instruction(sources, destinations);
saved_registers
}
Expand Down
3 changes: 1 addition & 2 deletions tooling/debugger/ignored-tests.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -16,5 +16,4 @@ scalar_mul
signed_comparison
simple_2d_array
to_bytes_integration
bigint
brillig_slices
bigint