Interfaces

Drv/CMakeLists.txt

@@ -1,6 +1,7 @@
 # Module subdirectories
 
 # Ports
+add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/Interfaces/")
 add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/Ports/")
 
 # Components

Drv/Interfaces/ByteStreamDriver.fpp

@@ -0,0 +1,18 @@
+module Drv {
+    interface ByteStreamDriver {
+        @ Port invoked when the driver is ready to send/receive data
+        output port ready: Drv.ByteStreamReady
+
+        @ Port invoked by the driver when it receives data
+        output port $recv: Drv.ByteStreamData
+
+        @ Invoke this port to send data out the driver
+        guarded input port $send: Fw.BufferSend
+
+        @ Port returning ownership of data received on $send port
+        output port sendReturnOut: Drv.ByteStreamData
+
+        @ Port receiving back ownership of data sent out on $recv port
+        guarded input port recvReturnIn: Fw.BufferSend
+    }
+}

Drv/Interfaces/CMakeLists.txt

@@ -0,0 +1,17 @@
+####
+# F prime CMakeLists.txt:
+#
+# SOURCE_FILES: combined list of source and autocoding files
+# MOD_DEPS: (optional) module dependencies
+#
+####
+register_fprime_module(
+    Drv_Interfaces
+  AUTOCODER_INPUTS
+    "${CMAKE_CURRENT_LIST_DIR}/ByteStreamDriver.fpp"
+    "${CMAKE_CURRENT_LIST_DIR}/Gpio.fpp"
+    "${CMAKE_CURRENT_LIST_DIR}/I2c.fpp"
+    "${CMAKE_CURRENT_LIST_DIR}/Spi.fpp"
+    "${CMAKE_CURRENT_LIST_DIR}/Tick.fpp"
+  INTERFACE
+)

Drv/Interfaces/Gpio.fpp

@@ -0,0 +1,12 @@
+module Drv {
+    interface Gpio {
+        @ Port used to write to a GPIO pin
+        sync input port gpioWrite: Drv.GpioWrite
+
+        @ Port used to read from a GPIO pin
+        sync input port gpioRead: Drv.GpioRead
+
+        @ Port used to indicate transition on the GPIO pin
+        output port gpioInterrupt: Svc.Cycle
+    }
+}

Drv/Interfaces/I2c.fpp

@@ -0,0 +1,12 @@
+module Drv {
+    interface I2c {
+        @ Port for guarded synchronous writing to I2C
+        guarded input port write: Drv.I2c
+
+        @ Port for guarded synchronous reading from I2C
+        guarded input port read: Drv.I2c
+
+        @ Port for synchronous writing and reading from I2C
+        guarded input port writeRead: Drv.I2cWriteRead
+    }
+}

Drv/Interfaces/Spi.fpp

@@ -0,0 +1,6 @@
+module Drv {
+    interface Spi {
+        @ Port to perform a synchronous read/write operation over the SPI bus
+        sync input port SpiReadWrite: Drv.SpiReadWrite
+    }
+}

Drv/Interfaces/Tick.fpp

@@ -0,0 +1,6 @@
+module Drv {
+    interface Tick {
+        @ The cycle outputs. Meant to be connected to rate group driver
+        output port CycleOut: Svc.Cycle
+    }
+}

Drv/LinuxGpioDriver/LinuxGpioDriver.fpp

@@ -1,7 +1,7 @@
 module Drv {
 
   passive component LinuxGpioDriver {
-    include "../Interfaces/GpioInterface.fppi"
+    import Gpio
 
 
     # ----------------------------------------------------------------------

Drv/LinuxI2cDriver/LinuxI2cDriver.fpp

@@ -1,9 +1,7 @@
 module Drv {
 
   passive component LinuxI2cDriver {
-    include "../Interfaces/I2cInterface.fppi"
-
-
+    import I2c
     }
 
 }

Drv/LinuxSpiDriver/LinuxSpiDriver.fpp

@@ -6,7 +6,7 @@ module Drv {
     # Interfaces
     # ----------------------------------------------------------------------
 
-    include "../../Drv/Interfaces/SpiInterface.fppi"
+    import Drv.Spi
 
     # ----------------------------------------------------------------------
     # Special ports

Drv/LinuxUartDriver/LinuxUartDriver.fpp

@@ -6,7 +6,7 @@ module Drv {
     # General ports
     # ----------------------------------------------------------------------
 
-    include "../Interfaces/ByteStreamDriverInterface.fppi"
+    import ByteStreamDriver
 
     @ Allocation port used for allocating memory in the receive task
     output port allocate: Fw.BufferGet

Drv/TcpClient/TcpClient.fpp

@@ -1,7 +1,7 @@
 module Drv {
     passive component TcpClient {
 
-        include "../Interfaces/ByteStreamDriverInterface.fppi"
+        import ByteStreamDriver
 
         @ Allocation for received data
         output port allocate: Fw.BufferGet

Drv/TcpServer/TcpServer.fpp

@@ -1,7 +1,7 @@
 module Drv {
     passive component TcpServer {
 
-        include "../Interfaces/ByteStreamDriverInterface.fppi"
+        import ByteStreamDriver
 
         @ Allocation for received data
         output port allocate: Fw.BufferGet

Drv/Udp/Udp.fpp

@@ -1,7 +1,7 @@
 module Drv {
     passive component Udp {
 
-        include "../Interfaces/ByteStreamDriverInterface.fppi"
+        import ByteStreamDriver
 
         output port allocate: Fw.BufferGet
 

FppTest/CMakeLists.txt

@@ -41,6 +41,7 @@ add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/component/")
 add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/dp/")
 add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/state_machine/")
 add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/enum/")
+add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/interfaces/")
 add_fprime_subdirectory("${CMAKE_CURRENT_LIST_DIR}/struct/")
 
 set(SOURCE_FILES "source.cpp")
@@ -52,6 +53,7 @@ set(MOD_DEPS
     ${PROJECT_NAME}/component/queued
     ${PROJECT_NAME}/dp
     ${PROJECT_NAME}/enum
+    ${PROJECT_NAME}/interfaces
     ${PROJECT_NAME}/state_machine/external_instance
     ${PROJECT_NAME}/state_machine/internal/initial
     ${PROJECT_NAME}/state_machine/internal/state

FppTest/component/active/active.fpp

@@ -2,13 +2,12 @@
 active component ActiveTest {
 
   include "../include/internal_ports.fppi"
-  include "../include/serial_ports.fppi"
-  include "../include/serial_ports_async.fppi"
-  include "../include/special_ports.fppi"
-  include "../include/typed_ports.fppi"
-  include "../include/typed_ports_async.fppi"
-
-  include "../include/output_ports.fppi"
+  import FppTest.SerialPorts
+  import FppTest.SerialPortsAsync
+  import FppTest.SpecialPorts
+  import FppTest.TypedPorts
+  import FppTest.TypedPortsAsync
+  import FppTest.OutputPorts
 
   include "../include/commands.fppi"
   include "../include/commands_async.fppi"