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[LoongArch] Introduce 32s target feature for LA32S ISA extensions #139695

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Merged
heiher merged 4 commits into from
May 20, 2025
Merged

[LoongArch] Introduce 32s target feature for LA32S ISA extensions #139695

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3ce7e72
[LoongArch] Introduce `32s` target feature for LA32S ISA extensions
heiher May 13, 2025
7940d1e
Support CPUCFG instruction for LA32R
heiher May 14, 2025
ba1adb9
Address xen0n's comments
heiher May 15, 2025
eef746e
Address wanglei's comments
heiher May 20, 2025
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9 changes: 6 additions & 3 deletions llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
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Expand Up @@ -854,6 +854,12 @@ def BREAK : MISC_I15<0x002a0000>;
def RDTIMEL_W : RDTIME_2R<0x00006000>;
def RDTIMEH_W : RDTIME_2R<0x00006400>;

// The CPUCFG instruction offers a reliable way to probing CPU features.
// Although it's undefined on LA32R, adding compiler support enables the
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@xen0n xen0n May 15, 2025 •
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Maybe this is better: "Although support is not guaranteed on LA32R, having compiler support nevertheless enables applications to rely on its presence, potentially via kernel emulation if not available natively."

(Apparently it's not forbidden to have it included in a LA32R implementation, it's just not in the mandatory set.)

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@heiher heiher May 15, 2025

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Looks good to me. 😃

// Linux kernel to emulate it, making the functionality available to user
// space applications.
def CPUCFG : ALU_2R<0x00006c00>;

// Cache Maintenance Instructions
def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12),
"$op, $rj, $imm12">;
Expand Down Expand Up @@ -895,9 +901,6 @@ def MASKNEZ : ALU_3R<0x00138000>;
// Branch Instructions
def BEQZ : BrCCZ_1RI21<0x40000000>;
def BNEZ : BrCCZ_1RI21<0x44000000>;

// Other Miscellaneous Instructions
def CPUCFG : ALU_2R<0x00006c00>;
} // Predicates = [Has32S]

/// LA64 instructions
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