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[LoongArch] Introduce 32s target feature for LA32S ISA extensions #139695

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Merged
heiher merged 4 commits into from
May 20, 2025
Merged

[LoongArch] Introduce 32s target feature for LA32S ISA extensions #139695

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3ce7e72
[LoongArch] Introduce `32s` target feature for LA32S ISA extensions
heiher May 13, 2025
7940d1e
Support CPUCFG instruction for LA32R
heiher May 14, 2025
ba1adb9
Address xen0n's comments
heiher May 15, 2025
eef746e
Address wanglei's comments
heiher May 20, 2025
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11 changes: 10 additions & 1 deletion llvm/lib/Target/LoongArch/LoongArch.td
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Original file line number Diff line number Diff line change
Expand Up @@ -14,9 +14,18 @@ include "llvm/Target/Target.td"

// LoongArch is divided into two versions, the 32-bit version (LA32) and the
// 64-bit version (LA64).

// LoongArch 32-bit is divided into two variants, the reduced 32-bit variant
// (LA32R) and the standard 32-bit variant (LA32S).
def Feature32S
: SubtargetFeature<"32s", "Has32S", "true",
"LA32 Standard Basic Instruction Extension">;
def Has32S : Predicate<"Subtarget->has32S()">;

def Feature64Bit
: SubtargetFeature<"64bit", "HasLA64", "true",
"LA64 Basic Integer and Privilege Instruction Set">;
"LA64 Basic Integer and Privilege Instruction Set",
[Feature32S]>;
def Feature32Bit
: SubtargetFeature<"32bit", "HasLA32", "true",
"LA32 Basic Integer and Privilege Instruction Set">;
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18 changes: 12 additions & 6 deletions llvm/lib/Target/LoongArch/LoongArchExpandAtomicPseudoInsts.cpp
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Expand Up @@ -214,8 +214,9 @@ static void doAtomicBinOpExpansion(const LoongArchInstrInfo *TII,
.addReg(ScratchReg)
.addReg(AddrReg)
.addImm(0);
BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQZ))
BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQ))
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@xen0n xen0n May 13, 2025

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BEQZ has the advantage over BEQ in that its reach is broader by 5 bits (width of a GPR slot), so if some of the changed bits potentially refers to a remote MBB, we may want to preserve them? I'm not looking at this code as closely as I'd prefer because I'm just battling my procrastination and doing a quick review here.

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@heiher heiher May 13, 2025

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I agree. While BEQZ does offer a wider branch range than BEQ, their latency and throughput are the same. For expanding the pseudo-atomic seqences, I believe BEQ's range is sufficient. I chose not to split it further to avoid unnecessary divergence between the 32-bit and 64-bit code paths.

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@xen0n xen0n May 15, 2025

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This is acceptable to me.

.addReg(ScratchReg)
.addReg(LoongArch::R0)
.addMBB(LoopMBB);
}

Expand Down Expand Up @@ -296,8 +297,9 @@ static void doMaskedAtomicBinOpExpansion(
.addReg(ScratchReg)
.addReg(AddrReg)
.addImm(0);
BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQZ))
BuildMI(LoopMBB, DL, TII->get(LoongArch::BEQ))
.addReg(ScratchReg)
.addReg(LoongArch::R0)
.addMBB(LoopMBB);
}

Expand Down Expand Up @@ -454,8 +456,9 @@ bool LoongArchExpandAtomicPseudo::expandAtomicMinMaxOp(
.addReg(Scratch1Reg)
.addReg(AddrReg)
.addImm(0);
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQZ))
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ))
.addReg(Scratch1Reg)
.addReg(LoongArch::R0)
.addMBB(LoopHeadMBB);

NextMBBI = MBB.end();
Expand Down Expand Up @@ -529,8 +532,9 @@ bool LoongArchExpandAtomicPseudo::expandAtomicCmpXchg(
.addReg(ScratchReg)
.addReg(AddrReg)
.addImm(0);
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQZ))
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ))
.addReg(ScratchReg)
.addReg(LoongArch::R0)
.addMBB(LoopHeadMBB);
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::B)).addMBB(DoneMBB);
} else {
Expand Down Expand Up @@ -569,8 +573,9 @@ bool LoongArchExpandAtomicPseudo::expandAtomicCmpXchg(
.addReg(ScratchReg)
.addReg(AddrReg)
.addImm(0);
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQZ))
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ))
.addReg(ScratchReg)
.addReg(LoongArch::R0)
.addMBB(LoopHeadMBB);
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::B)).addMBB(DoneMBB);
}
Expand Down Expand Up @@ -677,8 +682,9 @@ bool LoongArchExpandAtomicPseudo::expandAtomicCmpXchg128(
.addReg(ScratchReg)
.addReg(NewValHiReg)
.addReg(AddrReg);
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQZ))
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::BEQ))
.addReg(ScratchReg)
.addReg(LoongArch::R0)
.addMBB(LoopHeadMBB);
BuildMI(LoopTailMBB, DL, TII->get(LoongArch::B)).addMBB(DoneMBB);
int hint;
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22 changes: 22 additions & 0 deletions llvm/lib/Target/LoongArch/LoongArchISelDAGToDAG.h
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Expand Up @@ -64,6 +64,28 @@ class LoongArchDAGToDAGISel : public SelectionDAGISel {
bool selectVSplatUimmInvPow2(SDValue N, SDValue &SplatImm) const;
bool selectVSplatUimmPow2(SDValue N, SDValue &SplatImm) const;

// Return the LoongArch branch opcode that matches the given DAG integer
// condition code. The CondCode must be one of those supported by the
// LoongArch ISA (see translateSetCCForBranch).
static unsigned getBranchOpcForIntCC(ISD::CondCode CC) {
switch (CC) {
default:
llvm_unreachable("Unsupported CondCode");
case ISD::SETEQ:
return LoongArch::BEQ;
case ISD::SETNE:
return LoongArch::BNE;
case ISD::SETLT:
return LoongArch::BLT;
case ISD::SETGE:
return LoongArch::BGE;
case ISD::SETULT:
return LoongArch::BLTU;
case ISD::SETUGE:
return LoongArch::BGEU;
}
}

// Include the pieces autogenerated from the target description.
#include "LoongArchGenDAGISel.inc"
};
Expand Down
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