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[SPIRV][FPGA] Translate __fpga_reg builtin to FPGARegINTEL instruction #347

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[SPIRV][FPGA] Translate __fpga_reg builtin to FPGARegINTEL instruction #347

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1 change: 1 addition & 0 deletions llvm-spirv/lib/SPIRV/OCLUtil.h
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Original file line number Diff line number Diff line change
Expand Up @@ -165,6 +165,7 @@ const static char Dot[] = "dot";
const static char EnqueueKernel[] = "enqueue_kernel";
const static char FMax[] = "fmax";
const static char FMin[] = "fmin";
const static char FPGARegIntel[] = "__builtin_intel_fpga_reg";
const static char GetFence[] = "get_fence";
const static char GetImageArraySize[] = "get_image_array_size";
const static char GetImageChannelOrder[] = "get_image_channel_order";
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46 changes: 46 additions & 0 deletions llvm-spirv/lib/SPIRV/SPIRVReader.cpp
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Expand Up @@ -1756,6 +1756,52 @@ Value *SPIRVToLLVM::transValueWithoutDecoration(SPIRVValue *BV, Function *F,
case OpGetKernelNDrangeSubGroupCount:
return mapValue(
BV, transSGSizeQueryBI(static_cast<SPIRVInstruction *>(BV), BB));
case OpFPGARegINTEL: {
IRBuilder<> Builder(BB);

SPIRVFPGARegINTELInstBase *BC =
static_cast<SPIRVFPGARegINTELInstBase *>(BV);

PointerType *Int8PtrTyPrivate =
Type::getInt8PtrTy(*Context, SPIRAS_Private);
IntegerType *Int32Ty = Type::getInt32Ty(*Context);

Value *UndefInt8Ptr = UndefValue::get(Int8PtrTyPrivate);
Value *UndefInt32 = UndefValue::get(Int32Ty);

Constant *GS = Builder.CreateGlobalStringPtr(kOCLBuiltinName::FPGARegIntel);

Type *Ty = transType(BC->getType());
Value *Val = transValue(BC->getOperand(0), F, BB);

Value *ValAsArg = Val;
Type *RetTy = Ty;
auto IID = Intrinsic::annotation;
if (!isa<IntegerType>(Ty)) {
// All scalar types can be bitcasted to a same-sized integer
if (!isa<PointerType>(Ty) && !isa<StructType>(Ty)) {
RetTy = IntegerType::get(*Context, Ty->getPrimitiveSizeInBits());
ValAsArg = Builder.CreateBitCast(Val, RetTy);
}
// If pointer type or struct type
else {
IID = Intrinsic::ptr_annotation;
auto *PtrTy = dyn_cast<PointerType>(Ty);
if (PtrTy && isa<IntegerType>(PtrTy->getElementType()))
RetTy = PtrTy;
// Whether a struct or a pointer to some other type,
// bitcast to i8*
else {
RetTy = Int8PtrTyPrivate;
ValAsArg = Builder.CreateBitCast(Val, Int8PtrTyPrivate);
}
}
}

Value *Args[] = {ValAsArg, GS, UndefInt8Ptr, UndefInt32};
auto *IntrinsicCall = Builder.CreateIntrinsic(IID, RetTy, Args);
return mapValue(BV, IntrinsicCall);
}
default: {
auto OC = BV->getOpCode();
if (isSPIRVCmpInstTransToLLVMInst(static_cast<SPIRVInstruction *>(BV))) {
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51 changes: 37 additions & 14 deletions llvm-spirv/lib/SPIRV/SPIRVWriter.cpp
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Expand Up @@ -1322,6 +1322,22 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
return DbgTran->createDebugDeclarePlaceholder(cast<DbgDeclareInst>(II), BB);
case Intrinsic::dbg_value:
return DbgTran->createDebugValuePlaceholder(cast<DbgValueInst>(II), BB);
case Intrinsic::annotation: {
SPIRVType *Ty = transType(II->getType());

GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(II->getArgOperand(1));
if (!GEP)
return nullptr;
Constant *C = cast<Constant>(GEP->getOperand(0));
// TODO: Refactor to use getConstantStringInfo()
StringRef AnnotationString =
cast<ConstantDataArray>(C->getOperand(0))->getAsCString();

if (AnnotationString == kOCLBuiltinName::FPGARegIntel)
return BM->addFPGARegINTELInst(Ty, transValue(II->getOperand(0), BB), BB);

return nullptr;
}
case Intrinsic::var_annotation: {
SPIRVValue *SV;
if (auto *BI = dyn_cast<BitCastInst>(II->getArgOperand(0))) {
Expand All @@ -1332,6 +1348,7 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,

GetElementPtrInst *GEP = cast<GetElementPtrInst>(II->getArgOperand(1));
Constant *C = cast<Constant>(GEP->getOperand(0));
// TODO: Refactor to use getConstantStringInfo()
StringRef AnnotationString =
cast<ConstantDataArray>(C->getOperand(0))->getAsString();

Expand All @@ -1352,28 +1369,34 @@ SPIRVValue *LLVMToSPIRV::transIntrinsicInst(IntrinsicInst *II,
} else {
GI = dyn_cast<GetElementPtrInst>(II->getOperand(0));
}
SPIRVType *Ty = transType(GI->getSourceElementType());

SPIRVWord MemberNumber =
dyn_cast<ConstantInt>(GI->getOperand(2))->getZExtValue();

GetElementPtrInst *GEP = dyn_cast<GetElementPtrInst>(II->getArgOperand(1));
Constant *C = dyn_cast<Constant>(GEP->getOperand(0));
// TODO: Refactor to use getConstantStringInfo()
StringRef AnnotationString =
dyn_cast<ConstantDataArray>(C->getOperand(0))->getAsString();
dyn_cast<ConstantDataArray>(C->getOperand(0))->getAsCString();

std::vector<std::pair<Decoration, std::string>> Decorations =
parseAnnotations(AnnotationString);
if (GI) {
auto *Ty = transType(GI->getSourceElementType());
SPIRVWord MemberNumber =
dyn_cast<ConstantInt>(GI->getOperand(2))->getZExtValue();

if (Decorations.empty()) {
Ty->addMemberDecorate(new SPIRVMemberDecorateUserSemanticAttr(
Ty, MemberNumber,
AnnotationString.substr(0, AnnotationString.size() - 1)));
std::vector<std::pair<Decoration, std::string>> Decorations =
parseAnnotations(AnnotationString);

if (Decorations.empty()) {
Ty->addMemberDecorate(new SPIRVMemberDecorateUserSemanticAttr(
Ty, MemberNumber, AnnotationString));
} else {
addIntelFPGADecorationsForStructMember(Ty, MemberNumber, Decorations);
}
II->replaceAllUsesWith(II->getOperand(0));
} else {
addIntelFPGADecorationsForStructMember(Ty, MemberNumber, Decorations);
auto *Ty = transType(II->getType());
auto *BI = dyn_cast<BitCastInst>(II->getOperand(0));
if (AnnotationString == kOCLBuiltinName::FPGARegIntel)
return BM->addFPGARegINTELInst(Ty, transValue(BI, BB), BB);
}

II->replaceAllUsesWith(II->getOperand(0));
return 0;
}
default:
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4 changes: 3 additions & 1 deletion llvm-spirv/lib/SPIRV/libSPIRV/SPIRVEnum.h
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Expand Up @@ -117,7 +117,8 @@ enum SPIRVExtensionKind {
SPV_INTEL_blocking_pipes,
SPV_INTEL_device_side_avc_motion_estimation,
SPV_KHR_no_integer_wrap_decoration,
SPV_INTEL_fpga_memory_attributes
SPV_INTEL_fpga_memory_attributes,
SPV_INTEL_fpga_reg
};

typedef std::set<SPIRVExtensionKind> SPIRVExtSet;
Expand All @@ -128,6 +129,7 @@ template <> inline void SPIRVMap<SPIRVExtensionKind, std::string>::init() {
"SPV_INTEL_device_side_avc_motion_estimation");
add(SPV_KHR_no_integer_wrap_decoration, "SPV_KHR_no_integer_wrap_decoration");
add(SPV_INTEL_fpga_memory_attributes, "SPV_INTEL_fpga_memory_attributes");
add(SPV_INTEL_fpga_reg, "SPV_INTEL_fpga_reg");
}

template <> inline void SPIRVMap<SPIRVExtInstSetKind, std::string>::init() {
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23 changes: 23 additions & 0 deletions llvm-spirv/lib/SPIRV/libSPIRV/SPIRVInstruction.h
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Expand Up @@ -873,6 +873,29 @@ class SPIRVPhi : public SPIRVInstruction {
std::vector<SPIRVId> Pairs;
};

class SPIRVFPGARegINTELInstBase : public SPIRVInstTemplateBase {
public:
SPIRVCapVec getRequiredCapability() const override {
return getVec(CapabilityFPGARegINTEL);
}

SPIRVExtSet getRequiredExtensions() const override {
return getSet(SPV_INTEL_fpga_reg);
}

protected:
void validate() const override {
SPIRVInstruction::validate();

assert(OpCode == OpFPGARegINTEL &&
"Invalid op code for FPGARegINTEL instruction");
assert(getType() == getValueType(Ops[0]) && "Inconsistent type");
}
};

typedef SPIRVInstTemplate<SPIRVFPGARegINTELInstBase, OpFPGARegINTEL, true, 4>
SPIRVFPGARegINTEL;

class SPIRVCompare : public SPIRVInstTemplateBase {
protected:
void validate() const override {
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1 change: 1 addition & 0 deletions llvm-spirv/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
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Expand Up @@ -1002,6 +1002,7 @@ inline bool isValid(spv::Op V) {
case OpSubgroupAvcSicGetPackedSkcLumaCountThresholdINTEL:
case OpSubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL:
case OpSubgroupAvcSicGetInterRawSadsINTEL:
case OpFPGARegINTEL:
return true;
default:
return false;
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11 changes: 11 additions & 0 deletions llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.cpp
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Expand Up @@ -363,6 +363,8 @@ class SPIRVModuleImpl : public SPIRVModule {
SPIRVInstruction *addVectorInsertDynamicInst(SPIRVValue *, SPIRVValue *,
SPIRVValue *,
SPIRVBasicBlock *) override;
SPIRVInstruction *addFPGARegINTELInst(SPIRVType *, SPIRVValue *,
SPIRVBasicBlock *) override;

virtual SPIRVId getExtInstSetId(SPIRVExtInstSetKind Kind) const override;

Expand Down Expand Up @@ -1290,6 +1292,15 @@ SPIRVInstruction *SPIRVModuleImpl::addCopyMemorySizedInst(
BB);
}

SPIRVInstruction *SPIRVModuleImpl::addFPGARegINTELInst(SPIRVType *Type,
SPIRVValue *V,
SPIRVBasicBlock *BB) {
return addInstruction(
SPIRVInstTemplateBase::create(OpFPGARegINTEL, Type, getId(),
getVec(V->getId()), BB, this),
BB);
}

SPIRVInstruction *SPIRVModuleImpl::addVariable(
SPIRVType *Type, bool IsConstant, SPIRVLinkageTypeKind LinkageType,
SPIRVValue *Initializer, const std::string &Name,
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2 changes: 2 additions & 0 deletions llvm-spirv/lib/SPIRV/libSPIRV/SPIRVModule.h
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Expand Up @@ -375,6 +375,8 @@ class SPIRVModule {
SPIRVValue *,
SPIRVValue *,
SPIRVBasicBlock *) = 0;
virtual SPIRVInstruction *addFPGARegINTELInst(SPIRVType *, SPIRVValue *,
SPIRVBasicBlock *) = 0;
virtual SPIRVId getExtInstSetId(SPIRVExtInstSetKind Kind) const = 0;

// I/O functions
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1 change: 1 addition & 0 deletions llvm-spirv/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
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Expand Up @@ -490,6 +490,7 @@ template <> inline void SPIRVMap<Capability, std::string>::init() {
add(CapabilityFPGAMemoryAttributesINTEL, "FPGAMemoryAttributesINTEL");
add(CapabilityFPGALoopControlsINTEL, "FPGALoopControlsINTEL");
add(CapabilityBlockingPipesINTEL, "BlockingPipesINTEL");
add(CapabilityFPGARegINTEL, "FPGARegINTEL");
}
SPIRV_DEF_NAMEMAP(Capability, SPIRVCapabilityNameMap)

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1 change: 1 addition & 0 deletions llvm-spirv/lib/SPIRV/libSPIRV/SPIRVOpCodeEnum.h
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Expand Up @@ -431,3 +431,4 @@ _SPIRV_OP(SubgroupAvcSicGetPackedSkcLumaSumThresholdINTEL, 5815)
_SPIRV_OP(SubgroupAvcSicGetInterRawSadsINTEL, 5816)
_SPIRV_OP(ReadPipeBlockingINTEL, 5946)
_SPIRV_OP(WritePipeBlockingINTEL, 5947)
_SPIRV_OP(FPGARegINTEL, 5949)
2 changes: 2 additions & 0 deletions llvm-spirv/lib/SPIRV/libSPIRV/spirv.hpp
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Expand Up @@ -681,6 +681,7 @@ enum Capability {
CapabilityFPGAMemoryAttributesINTEL = 5824,
CapabilityFPGALoopControlsINTEL = 5888,
CapabilityBlockingPipesINTEL = 5945,
CapabilityFPGARegINTEL = 5948,
CapabilityMax = 0x7fffffff,
};

Expand Down Expand Up @@ -1127,6 +1128,7 @@ enum Op {
OpSubgroupAvcSicGetInterRawSadsINTEL = 5816,
OpReadPipeBlockingINTEL = 5946,
OpWritePipeBlockingINTEL = 5947,
OpFPGARegINTEL = 5949,
OpMax = 0x7fffffff,
};

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