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Fix preallocated bridge_port_list size #256

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Merged
stcheng merged 3 commits into from
Jul 18, 2017
Merged

Fix preallocated bridge_port_list size #256

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4d1d67f
Fix preallocated bridge_port_list size
qiluo-msft Jul 18, 2017
c0b4a06
Revert "[copporch]: Add UDLD entry in COPP (#252)": now Mellanox
qiluo-msft Jul 18, 2017
f4ba192
(add FIXME comment)
qiluo-msft Jul 18, 2017
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1 change: 0 additions & 1 deletion orchagent/copporch.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -42,7 +42,6 @@ map<string, sai_hostif_trap_type_t> trap_id_map = {
{"igmp_v2_report", SAI_HOSTIF_TRAP_TYPE_IGMP_TYPE_V2_REPORT},
{"igmp_v3_report", SAI_HOSTIF_TRAP_TYPE_IGMP_TYPE_V3_REPORT},
{"sample_packet", SAI_HOSTIF_TRAP_TYPE_SAMPLEPACKET},
{"udld", SAI_HOSTIF_TRAP_TYPE_UDLD},
{"switch_cust_range", SAI_HOSTIF_TRAP_TYPE_SWITCH_CUSTOM_RANGE_BASE},
{"arp_req", SAI_HOSTIF_TRAP_TYPE_ARP_REQUEST},
{"arp_resp", SAI_HOSTIF_TRAP_TYPE_ARP_RESPONSE},
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4 changes: 3 additions & 1 deletion orchagent/portsorch.cpp
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Expand Up @@ -177,7 +177,9 @@ void PortsOrch::removeDefaultVlanMembers()
void PortsOrch::removeDefaultBridgePorts()
{
/* Get bridge ports in default 1Q bridge */
vector<sai_object_id_t> bridge_port_list(m_portCount);
// FIXME: Mellanox SAI implementation will response SAI_BRIDGE_ATTR_PORT_LIST
// all the front panel ports and CPU port. The CPU bug should be there by SAI spec.
vector<sai_object_id_t> bridge_port_list(m_portCount + 1);

sai_attribute_t attr;
attr.id = SAI_BRIDGE_ATTR_PORT_LIST;
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