wrong code regression: HashSet initialization

[Dushistov]

Idea of bug is simple:

use std::collections::HashSet;

#[derive(PartialEq, Debug, Hash, Eq, Clone)]
enum SentenceType {
    None,
    AAM,
    //...many
    RMC,
    GGA,
    //..many
}

fn f(s: HashSet<SentenceType>) {
    println!("s: {:?}", s);
}

fn main() {
    f([SentenceType::RMC, SentenceType::GGA]
          .iter()
          .cloned()
          .collect());
}

On stable today compiler rustc 1.18.0 (03fc9d622 2017-06-06) it print as expected {RMC, GGA}, but if use beta/nightly it prints all variants from SentenceType.

Note: that the code above is just sketch, to realy reproduce problem you need android/arm cpu (may be works with other/arm, but I not able to check right now),
and two crates, in attachment crate that reproduce problem,
to run it you may use such commands:

adb shell mkdir /data/sample
cargo build   --target=arm-linux-androideabi --release
adb push target/arm-linux-androideabi/release/hashset_bug /data/sample/
adb shell 'RUST_LOG=debug /data/sample/hashset_bug'

With stable it produces such output:

DEBUG:hashset_bug: Hello, world!
DEBUG:nmea: create_for_navigation-beta: arg {RMC, GGA}
DEBUG:nmea: create_for_navigation: our {RMC, GGA}

with beta/nightly it prodcues such output:

DEBUG:hashset_bug: Hello, world!
DEBUG:nmea: create_for_navigation-beta: arg {MTW, GTD, DSI, ZDL, RMB, MWD, DSR, TUT, ZDA, RSA, HSC, CUR, RSD, OLN, XDR, RTE, ABK, DBK, SFI, HDG, BWR, GRS, DTM, LRF, MWV, ACA, TLB, HTD, SSD, GSV, RMA, MSK, APB, MSS, GLC, HDT, WCV, VHW, ACK, MLA, ASD, GXA, RMC, APA, ZFO, LR3, GNS, AAM, ZTG, GGA, FSI, BWW, XTR, VPW, AIR, VWR, XTE, BWC, LRI, BEC, TTM, LR2, LCD, ROT, VDO, GBS, GMP, VDR, GSA, RPM, ALM, VSD, GST, TRF, LR1, DCN, VDM, DPT, TXT, VLW, HMR, DSE, None, VBW, BOD, GLL, VTG, DBS, WNC, TLL, ACS, DSC, ALR, STN, DBT, HMS, HDM}
DEBUG:nmea: create_for_navigation: our {MTW, GTD, DSI, ZDL, RMB, MWD, DSR, TUT, ZDA, RSA, HSC, CUR, RSD, OLN, XDR, RTE, ABK, DBK, SFI, HDG, BWR, GRS, DTM, LRF, MWV, ACA, TLB, HTD, SSD, GSV, RMA, MSK, APB, MSS, GLC, HDT, WCV, VHW, ACK, MLA, ASD, GXA, RMC, APA, ZFO, LR3, GNS, AAM, ZTG, GGA, FSI, BWW, XTR, VPW, AIR, VWR, XTE, BWC, LRI, BEC, TTM, LR2, LCD, ROT, VDO, GBS, GMP, VDR, GSA, RPM, ALM, VSD, GST, TRF, LR1, DCN, VDM, DPT, TXT, VLW, HMR, DSE, None, VBW, BOD, GLL, VTG, DBS, WNC, TLL, ACS, DSC, ALR, STN, DBT, HMS, HDM}

hashset_bug.zip

[nikomatsakis]

Nominating. cc @rust-lang/compiler -- anybody have any ideas what's going on with this ARM codegen regression?

[Mark-Simulacrum]

So we've updated to LLVM 4.0.1 since then (#42930) -- I suspect that may well have fixed this problem. Perhaps @Dushistov could check on a recent nightly? In case the problem isn't quite fixed, cc @arielb1