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By MOSI/MISO missing I'm guessing you mean using the |
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So we provide SPI implementation without owning the MISO pin? The potential problem I see here is that SPI traits usually deal with reading and writing. Maybe we need to re-structure the trait implementation to return errors in those pin configurations that are not complete (e.g., return an Error when trying to read from a display) |
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I rescued a few examples from In any case, I will try to set up a proper GDB session with semihosting so we can test examples on board. Eventually, QEMU will support our needs and we can start using more robust CI workflows. |
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I added new examples. It looks like QEMU supported GPIOs, but I introduced a bug in the GPIO implementation. Current examples work as expected both in QEMU and on board. Examples are now in I managed to use semihosting on the board. However, it only works for OpenOCD, JLinkDebugger has this option disabled. |
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I still need to check:
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@almindor all the |
almindor
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This was a huge amount of work! Thank you!
Do you want to do a 0.11 release right after this is merged? |
NOTE: I still haven't tested these updates on boards. I will keep building some examples to verify that everything is alright. Furthermore, I have a few doubts about some peripherals (especially SPI, namely I don't understand why we would support SPI peripherals with MOSI or MISO missing).