Skip to content

Conversation

@fischeti
Copy link
Contributor

@fischeti fischeti commented Dec 1, 2025

The serial link received the SystemRDL treatment among other improvents for integration & parametrization

TODO:

  • Fix missing _reserved_Xx_Yy field names if non-default configurations are used.
  • Create and reference a new major release of serial_link once this PR is approved.
  • Maybe wait for clint: systemRDL based register generation #252 to be merged/discussed.
  • Update peakrdl-regblock package in Gitlab CI python environment.
  • Gitlab CI: fix ERROR: Cannot start server on port 3042: already in use. errors during FPGA boot jobs.

@fischeti fischeti marked this pull request as ready for review December 5, 2025 08:54
@fischeti fischeti requested review from creinwar and paulsc96 December 5, 2025 08:54
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Labels

None yet

Projects

None yet

Development

Successfully merging this pull request may close these issues.

2 participants