This project was completed in collaboration with Rónán Loftus in which we implemented a custom RISC-V assembly instruction and extended the ALU, decoder and the processor so that this instruction could be supported.
The instruction has the following structure:
txfr rd, rs1, rs2
Where rs1 is a control register, rs2 is the source register and rd is the destination register. The data in rs2 is rearranged in accordance with rs1 and stored in rd.