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    8 repositories

    • veriloggen

      Public
      Veriloggen: A Mixed-Paradigm Hardware Construction Framework
      pythoncompilerhardwareverilog-hdlpyveriloghigh-level-synthesishardware-construction-language
      Python
      •
      Apache License 2.0
      •59•325•25•1•Updated Aug 10, 2024Aug 10, 2024

    • Pyverilog

      Public
      Python-based Hardware Design Processing Toolkit for Verilog HDL
      pythonparsercode-generatorcompilerhardwareverilog-hdldataflow-analyzercontrol-flow-analyzer
      Python
      •
      Apache License 2.0
      •210•768•74•7•Updated Jun 15, 2024Jun 15, 2024

    • hardcheck

      Public
      Automatic Hardware Design Translator for Checkpointing and Live Migration on FPGAs
      Python
      •
      Other
      •0•2•0•0•Updated Feb 7, 2019Feb 7, 2019

    • ipgen

      Public
      IP-core package generator for AXI4/Avalon
      Python
      •
      Other
      •6•22•1•0•Updated Nov 25, 2018Nov 25, 2018

    • zynq-linux

      Public
      How to configure Debian Linux environment for Xilinx Zynq.
      C
      •12•32•0•0•Updated Jan 5, 2017Jan 5, 2017

    • PyCoRAM

      Public
      Python-based Portable IP-core Synthesis Framework for FPGA-based Computing
      Python
      •
      Other
      •10•53•2•0•Updated Nov 21, 2016Nov 21, 2016

    • flipSyrup

      Public
      Cycle-Accurate Hardware Simulation Framework on Abstract FPGA Platforms
      Verilog
      •
      Other
      •4•8•0•0•Updated Mar 7, 2016Mar 7, 2016

    • mulpy

      Public
      MULPY: A Multi-Paradigm High-Level Hardware Design Framework in Python
      Python
      •
      Other
      •0•1•0•0•Updated Feb 17, 2016Feb 17, 2016