feat(perf): Remove redundant inc rc without instructions between

[vezenovm]

Description

Problem*

Part of general effort to reduce Brillig bytecode sizes.

Summary*

We often have patterns like such (example from brillig_rc_regression_6123):

brillig fn main f0 {
  b0():
    inc_rc [Field 0, Field 0]
    inc_rc [Field 0, Field 0]
    inc_rc [Field 0, Field 0]
    inc_rc [Field 0, Field 0]
    inc_rc [Field 0, Field 0]
    v4 = allocate
    store [Field 0, Field 0] at v4
    v5 = allocate
    store u32 0 at v5
    inc_rc [Field 0, Field 0]
    v7 = allocate
    store [Field 0, Field 0] at v7
    inc_rc [Field 0, Field 0]
    inc_rc [Field 0, Field 0]
    jmp b1(u32 0)

It is usually due to each impl method that mutably borrows self placing inc RCs on the internal arrays of the struct for which it is implementing the method. Without any instructions in between these inc_rc instructions, we can safely collapse the inc_rcs into a single one.

The SSA was brillig_rc_regression_6123 now looks like such:

brillig fn main f0 {
  b0():
    inc_rc [Field 0, Field 0]
    v4 = allocate
    store [Field 0, Field 0] at v4
    v5 = allocate
    store u32 0 at v5
    inc_rc [Field 0, Field 0]
    v7 = allocate
    store [Field 0, Field 0] at v7
    inc_rc [Field 0, Field 0]
    jmp b1(u32 0)

This PR does a slight refactor as the track_inc_rcs_to_remove was starting to take a lot of parameters. I made a new RcTracker struct. Its state is simply updated per instruction as previously and then the instructions it marks for removal are including at the end of performing DIE on a block.

Additional Context

Documentation*

Check one:

• No documentation needed.
• Documentation included in this PR.
• [For Experimental Features] Documentation to be submitted in a separate PR.

PR Checklist*

• I have tested the changes locally.
• I have formatted the changes with Prettier and/or cargo fmt on default settings.