Rewording LLVM backend requirements in what.rst

[hms0411rt]

Make it clear that only AVX512 ISA FMA ISA CPUs are supported on x86 for LLVM backends. Is ORCv2 or MCJIT another requirement? Maybe add some of the checks done by jitc_llvm_init() to the documentation or to a requirements section.

[wjakob]

The vector instruction sets are not required. Dr.Jit/LLVM will use them when available to provide performance improvements, but they are definitely not a prerequisite.

[hms0411rt]

@wjakob I need the LLVM backend for Sionna-RT but I cannot import drjit without the error jit_llvm_init(): your CPU does not support the `fma` instruction set, shutting down the LLVM backend... as my CPU is too old. Should I open an issue instead?

[lnuic]

@hms0411rt this is related to mitsuba-renderer/drjit-core#60. You can probably patch drjit-core in a similar way to mitsuba-renderer/drjit-core#59 to make it work, but I don’t think there’s a plan to officially support it.

[hms0411rt]

Thanks for the patch @lnuic, I will try that.

Should the documentation then state that x86 ivy bridge and older are not officially supported? Potentially with a reference to the patch.

And do I read llvm_core.cpp correctly that having ORCv2 or MCJIT is another requirement?

    if (jitc_llvm_api_has_orcv2() && jitc_llvm_orcv2_init()) {
        jitc_llvm_use_orcv2 = true;
    } else if (jitc_llvm_api_has_mcjit() && jitc_llvm_mcjit_init()) {
        jitc_llvm_use_orcv2 = false;
    } else {
        jitc_log(Warn, "jit_llvm_init(): ORCv2/MCJIT could not be initialized, "
                       "shutting down LLVM backend..");
        jitc_llvm_shutdown();
        return false;
    }

[hms0411rt]

@wjakob @lnuic can we reopen the PR to add the comment on FMA?

I am new to git, should I amend and force push my modifications from another commit?