Vendor in latest OpenTitan IPs #2339
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…/0001-PATCH-Change-RAM-DFT-signals.patch
…/0004-PATCH-Add-rst-to-prim_ram_1p.patch
Update code from upstream repository https://github.com/lowRISC/opentitan to revision 3424e7fb4bc3ac92eb640d6af070055d293bc710 * [dv] Avoid passing default name/parent to uvm_component constructors (Rupert Swarbrick) * [prim] Add a prim_pkg to define technology primitive specific parameters (Robert Schilling) * [hw,prim_rom,rtl] Move rvalid in prim_rom instead of generating it (Robert Schilling) * [hw,prim,rtl] prim_rst_sync might have a technology-dependent implementation for DFT (Robert Schilling) * [lint] Waive too long lines on ral_pkg (Robert Schilling) * [pwm,dv] fix include path (Michael Gautschi) * [utils] Add python script to find potential issues in netlist (Michael Gautschi) * [hw/prim] Addition of prim_sdc_example for constraints checking (Michael Gautschi) * [hw,prim_sha2,rtl] Add missing includes of prim_assert.h (Robert Schilling) * [hw,prim_intr_hw,rtl] Add missing includes of prim_assert.h (Robert Schilling) * [alert,fpv] Fix the AlertPingOk_A assertion for async alerts (Rupert Swarbrick) * [dv] Add uvm_object_utils call to dv_report_server (Rupert Swarbrick) * [dv] Make it possible for a sequence to copy information to children (Rupert Swarbrick) * [prim] Add parameter to control saturation behavior of prim_sum_tree (Pirmin Vogel) * [dv] Allow a test to add extra sequencers to a virtual sequence (Rupert Swarbrick) * [prim,fpv] Make HungHandShake_A and ReqTimeout_A bounded assertions (Rupert Swarbrick) * [seeds] Rename dev to testing seed (Robert Schilling) * [c++17,hw] Update hw/ to use C++17 on Master (Collin MacDonald) * [c++,hw] Update hw/ to use C++17 (Collin MacDonald) * [dv] Add an access lock to dv_base_reg (Rupert Swarbrick) * [topgen] Add a per-top seed configuration (Robert Schilling) * [corefiles] Properly use prim_legacy_pkg and remove virtual chip_env core (Robert Schilling) * [prim,fpv] Avoid prim_clock_mux2 using $isunknown in FPV (Rupert Swarbrick) * [chip, dv] Added a switch to get different randomization per instance (Kinza Qamar) * [prim] remove $clog2 workaroud for Xcelium < 19.10 (Gary Guo) * [dv] Downgrade more errors when building vcs simv with newer compilers (Harry Callahan) * [alert,fpv] Add missing definitions of SkewCycles in FPV tbs (Rupert Swarbrick) * [hw,prim_sha2,lint] Remove wildcard waiver on *reg_top.sv (Robert Schilling) * [hw,prim_alert,dv] Add 3 cycles clock skew to the testbench config (Robert Schilling) * [membkdr] Provide a tile adapter to access internal rows (Robert Schilling) * [hw,ips,rtl] Use SkewCycles in prim_esc_(sender|receiver) (Robert Schilling) * [hw,ips,rtl] Expose SkewCycles parameter on all comportable IPs (Robert Schilling) * [prim_(alert|esc)_(sender|receiver),rtl] Integrate SkewCycles parameter (Robert Schilling) * [hw,prim_diff_decode,rtl] Support for parametrizable skew between diff pair (Robert Schilling) * Fixes utils.py for missed .name (Chih-Hsueh "Josh" Huang) * [prim,doc] Expand prim/README.md to add more context and examples (Harry Callahan) * [util,cleanup] Fix typos in misc comments/docs (Elliot Baptist) * [dvsim,cleanup] Fix typos in comments/docs (Elliot Baptist) * [membkdr_util] Support for custom tile suffix (Robert Schilling) * [hw,prim_edge_detector,lint] Remove unused waiver inclusion (Robert Schilling) * [util,secded_gen] Support parameterized secded instantiation (Guillermo Maturana) * [dv] Fix typo dv_fcov_macros.svh (Elliot Baptist) * [dv] Fix common typo in env_cov files (Elliot Baptist) * [dv] Fix common typo in scoreboards (Elliot Baptist) * [tlul, prim] Fix typos in typos fix (Elliot Baptist) * [dvsim,hjson] Remove all dead code 'design_level' references/overrides (Harry Callahan) * [doc] Fix links and typos for some DV docs (Martin Velay) * [prim,doc] Updated the main documentation for the post primgen world (Hugo McNally) * [prim,doc] Edited main page to conform to style guide. (Hugo McNally) * [dv] Fix typos in comments/docs (Elliot Baptist) * [prim,tlul] Fix typos in comments (Elliot Baptist) * [dv] Downgrade error when building vcs simv with newer compiler builds (Harry Callahan) * [dv] Allow unsupported OS when running jg for UNR (Harry Callahan) * [doc] Replace some https links with relative paths (Elliot Baptist) * [doc] Update old docs.opentitan links (Elliot Baptist) * [prim, rtl] Deadcode else statement when state_q is IsStd (Kinza Qamar) * [hw,prim_flop_no_rstm,rtl] Fixup generic RTL implementation (Robert Schilling) * [hw,prim,corefile] Remove dangling prim_flop_no_rst core file (Robert Schilling) * [flash] Move assertion from `flash_ctrl` to `prim_flash` (Andreas Kurth) * [dv, push_pull_monitor] call super. in run_phase (Antonio Martinez Zambrana) * [dv, push_pull_agent_cov] call super. in build_phase (Antonio Martinez Zambrana) * [dv, push_pull_agent] call super. in run_phase (Antonio Martinez Zambrana) * [dv, dv_base_vseq] Remove uvm_fatal from the body (Antonio Martinez Zambrana) * [dv, dv_base_test] call super. in run_phase (Antonio Martinez Zambrana) * [dv, dv_base_monitor] call super. in run_phase (Antonio Martinez Zambrana) * [dv, dv_base_driver] call super. in run_phase (Antonio Martinez Zambrana) * [rv_timer, verissimo] UVM new() function (Kinza Qamar) * [dv, dv_utils_pkg] Add full_name to UVM reporting macros (Antonio Martinez Zambrana) * [dv, csr_utils_pkg] Add full_name to UVM reporting macros (Antonio Martinez Zambrana) * [dv, dv_base_reg] Add full_name to UVM reporting macros (Antonio Martinez Zambrana) * [dv] Rewrite verilator_memutil.cc to avoid exceptions (Rupert Swarbrick) * [doc] Include image files in doc build (James Wainwright) * [bazel] Add `doc_files` groups for mdbook sources (James Wainwright) * [prim_*] Leave macros out of prim_generic:all (Hugo McNally) * [prim] Rename all files to match virtual cores (Hugo McNally) * [prim] Replace primgen with virtual prim cores (Hugo McNally) * [otp_macro] Clean up straggling core (Hugo McNally) * [dv] Pass "id" more cleanly to error messages in dv_utils_pkg (Rupert Swarbrick) * [dv] Use `gfn in dv_base_env_cfg::create_ral_by_name (Rupert Swarbrick) * [dv] Tidy up id argument for uvm_fatal in dv_base_reg_pkg.sv (Rupert Swarbrick) * [dv] Use `gfn in dv_base_mem (Rupert Swarbrick) * [dv] Tidy up id argument for uvm_info calls in csr_utils_pkg (Rupert Swarbrick) * [prim,fpv] Fix width warnings in prim_fifo_sync_assert_fpv (Rupert Swarbrick) * [hw,prim] Include `flop_no_rst` to `:all` core file (Hugo McNally) * [ipgen] Fix missing deps for various reg tops (Alexander Williams) * [rtl,prim] Add a missing dependency on prim:count (Rupert Swarbrick) * [prim,rtl] Add a NeverClears parameter to prim_fifo_sync(_cnt) (Rupert Swarbrick) * [prim,rtl] Pass PossibleActions parameter inside prim_fifo_sync_cnt (Rupert Swarbrick) * [hw,prim_diff_flop,rtl] No generic instantiation of prim_flop_2sync (Robert Schilling) * [hw,prim_subreg,rtl] Assert qe only on SW writes (Robert Schilling) * [hw,dv_base_reg_block,dv] Fix Xcelium 24.09 warning of passing a string to an int arg (Robert Schilling) * [rtl,sec] Define more precise version of ASSERT_ERROR_TRIGGER_ALERT (Rupert Swarbrick) * [prim_lfsr, Xcelium] Function called as a task without 'void() (Kinza Qamar) * [dv] Simplify use of dv_base_reg::atomic_en_shadow_wr (Rupert Swarbrick) * [dv] Constant-initialise a dynamic array more nicely (Rupert Swarbrick) * [dv] Add a GUI debug mode for Riviera (Dariusz Stachanczyk) * [racl] Add generic RACL testplan (Robert Schilling) * [top,otp_macro] Move prim_otp out of otp_ctrl (Guillermo Maturana) * [format,flash_ctrl] Format flash_ctrl core per verible-verilog- format (Guillermo Maturana) * [rtl,flash_ctrl] Create top specific package (Guillermo Maturana) * [prim,rtl] Avoid using inside in a constant expression (Rupert Swarbrick) * [dv] Correct foreach syntax in dv_report_catcher (Rupert Swarbrick) * [prim_alert] Permit testing with xcelium (Adrian Lees) * [corefiles] Let top_racl_pkg depend on concrete top_pkg (Robert Schilling) * [darjeeling] Fix undriven input ports (Adrian Lees) * [dv] Fix uvm_component_param_utils call in dv_base_monitor (Rupert Swarbrick) * [sw] disable clang-format in all vendor directories (James Wainwright) * [hw,prim_diff,rtl] Use _po/_no and _pi/_ni suffix (Robert Schilling) * [hw,prim_diff_to_alert,rtl] Fix RTL bugs that were not linted! (Robert Schilling) * [hw,sram_ctrl,rtl] Ability to correct single-bit errors and log error (Robert Schilling) * [hw,alert2diff,rtl] Add prims to translate between alerters and differential signals (Robert Schilling) * [hw,prim_diff_encode,rtl] Add primitive to differentially encode a signal (Robert Schilling) * [dvsim] Add -fs option for --fixed-seed (Martin Velay) * [dv] Check types properly in DV_EOT_PRINT_TLM_FIFO_CONTENTS (Rupert Swarbrick) * [dv] Simplify DV_EOT_PRINT_TLM_FIFO_CONTENTS macro (Rupert Swarbrick) * [fusesoc,otp_ctrl] Change otp_ctrl_prim_reg_top core to template (Guillermo Maturana) * [dv,sv] Fix simple typos (Guillermo Maturana) * [hw,ram,params] is not synthesizable, drop it... (Robert Schilling) * [dv_utils] Fix and improvements (Martin Velay) * [tools,ipgen] Improve VLNV renaming (Guillermo Maturana) * [dvsim] Fix dvsim makefile for Darjeeling bring up (Adrian Lees) * [dv] Remove m_access from dv_base_mem (Rupert Swarbrick) * [dv] Reorder dv_base_mem to use out-of-block definitions (Rupert Swarbrick) * [prim] Add mubix_logic_test_true_strict function (Martin Velay) * [hw,prim_xilinx_ram_1p,rtl] Don't use string, the tools don't like it (Robert Schilling) * [prim,dv] Fix a failure mode for ASSERT_FPV_LINEAR_FSM (Rupert Swarbrick) * [dv]Minor update in the base sequencer class (Marcelo Carvalho Faleiro de Almeida) * [tool,doc] Fix path to uvmdvgen in README file (Rupert Swarbrick) * [hw,ac_ranges,rtl] Compute denied range index using PPC (Robert Schilling) * [darjeeling] Changes to support Darjeeling bring up (Adrian Lees) * [racl] Distribute access address on RACL error (Robert Schilling) * [hw,prim_xilinx_ram_1p] Explicitly cast MemInitFile to string (Robert Schilling) * Included functions to dv_base_virtual_sequencer (Marcelo Carvalho Faleiro de Almeida) * [dv,mem_bkdr_util] Separate out ROM, SRAM and flash-specific behavior (Adrian Lees) * [python] Move uvmdvgen out of its own package (James Wainwright) * [dvsim] fix bug in busy launcher reschedule strategy (James McCorrie) * [prim,rtl] Get rid of a trivial combinatorial variable (Rupert Swarbrick) * [prim,rtl] Rewrite a case as if/else to avoid unreachable case (Rupert Swarbrick) * [prim] Add flop without reset (Robert Schilling) * [python] Apply Ruff auto-fixes (James Wainwright) * [python] Remove importlib_resources polyfill (James Wainwright) * [python] Resolve bodges for old Python versions (James Wainwright) * [racl] Add an error log arbiter primitive (Robert Schilling) * [dvsim] more robust local launcher process management (James McCorrie) * [dvsim] Lint fixes (James McCorrie) * [fusesoc] Move all cores under the hw directory (Alexander Williams) * [membkdr] Pass tiling parameters from sram bkdr util down (Robert Schilling) * [membkdr] read32 only return 32-bit (Robert Schilling) * [dd, prim] Simplyfing condition to ease coverage closure (Antonio Martinez Zambrana) * [prim_xilinx,englishbreakfast] Remove ROM dependency (Alexander Williams) * [dd, prim_reg_cdc_arb] state signal width reduction (Antonio Martinez Zambrana) * [dv,mem_bkdr_util] Memory back door specializations (Adrian Lees) * [rtl, prim_reg_cdc_arb] Conditional coverage simplification (Antonio Martinez Zambrana) * [hw,prim_subreg_shadow,rtl] Add Mubi Support to prim_subreg_shadow (Robert Schilling) * [hw,prim_generic_ram_1r1w,lint] Rename signal in waiver that changed in RTL (Robert Schilling) * [prim_ram_1r1w_async_adv,lint] rst_a/b_ni are legal async reset (Robert Schilling) * [hmac, rtl] Increase coverage through minor RTL restructure (Andrea Caforio) * [membkdr] Add support for bkdr preloading (Robert Schilling) * [membkdr] Switch to uint32_t in constructor (Robert Schilling) * [membkdr] Add RAM tiling to membkdr utility (Robert Schilling) * [hw,otp_ctrl,rtl] Parametrize the DFT config and response port (Robert Schilling) * [hmac,dv] Allow reset w/o CSR accesses complete (Martin Velay) * [prim,rtl] Remove ~under_rst from the expression for fifo_incr_wptr (Rupert Swarbrick) * [hw,otp_ctrl,rtl] Provide a DFT config and response port (Robert Schilling) * [bazel,hw] exclude DV files from hw/ip/*/BUILD globs (Gary Guo) * [hw] remove unneeded DV dependencies (Gary Guo) * [dv,mem_bkdr_util] Move otp specific code to otp_ctrl (Guillermo Maturana) * [mem_bkdr_util] Temporarily fix build for an otp_ctrl parameter (Rupert Swarbrick) * [rom_ctrl, dv] Conditional coverage hole in tlul_adapter_sram fifos (Kinza Qamar) * [ipgen,otp_ctrl] Change otp_ctrl to ipgen (Guillermo Maturana) * [flash_ctrl] Uniquify VLNVs and clean up core hierarchy (Alexander Williams) * [prim] Add hacky prim_flop dependency to prim_flop_2sync (Alexander Williams) * [prim_mubi] Split off constants to prim_mubi_pkg core (Alexander Williams) * [dv, base_reg] Adding a prediction flag to field and mask to reg (Antonio Martinez Zambrana) * [hmac,dv] Wipe secret assertions (Martin Velay) * [prim_fifo_sync,rtl] Specialize for Depth == 1 (Rupert Swarbrick) * [prim_generic] Depened on the tech ram_pkg within the tech lib (Robert Schilling) * [hw,prim_ram_1r1w,rtl] Fix DFT response port (Robert Schilling) * [hw,prim_generic_ram_1r1w,rtl] Add reset inputs (Robert Schilling) * [hw,prim_ram,rtl] Make default assignment and not reference struct (Robert Schilling) * [hw,prim_rom_pkg,rtl] Move prim_rom_pkg to tech-lib (Robert Schilling) * [prim_ram_1p] Ram tiling for sram_ctrl and prim_ram_1p (Robert Schilling) * [hw,prim_ram_1p,rtl] Add reset input to prim_ram_1p (Robert Schilling) * [hw,prim,ram_2p] Add DFT response channel (Robert Schilling) * [hw,prim,ram_1p] Add DFT response channel (Robert Schilling) * [prim/doc] Add pointer to hardened Keccak implementation in prim_keccak (Pirmin Vogel) * [hw,prim_rom,rtl] Add reset input to prim_rom (Robert Schilling) * [hmac, rtl] Do not skip padding after a hash stop command (Andrea Caforio) * [prim,earlgrey,fpga] Add specialized ram_1p prim (Alexander Williams) * [dv] Be more careful not to leave orphan processes in clk_rst_if (Rupert Swarbrick) * [hmac,rtl] Fix hang after stop lowRISC/opentitan#24767 (Martin Velay) * [dv] Fix DVSim after GUI_DEBUG addition (Martin Velay) * [prim,rtl] Rewrite a loop to avoid needing signed values (Rupert Swarbrick) * [prim,lint] Remove dead waivers for prim_fifo_*sync.sv (Rupert Swarbrick) * [prim,rtl] Remove dead code in prim_fifo_async_sram_adapter (Rupert Swarbrick) * [prim,lint] Remove waiver for prim_subreg.sv (Rupert Swarbrick) * [prim,lint] Remove waiver for prim_sram_arbiter.sv (Rupert Swarbrick) * [prim,rtl] Rephrase a term in prim_reg_cdc.sv (Rupert Swarbrick) * [prim,fpv] Connect and check err_o for prim_fifo_sync (Rupert Swarbrick) * [prim,fpv] Connect and check full_o (Rupert Swarbrick) * [prim_fifo_sync,rtl] Fix full_o behaviour when Depth == 0 (Rupert Swarbrick) * [hw,prim_ram_1r1w,lint] Add lint rule for input not read (Robert Schilling) * [hw,prim_ram_1r1w,lint] rst_a_ni is only used in assertions in some configs (Robert Schilling) * [prim] Exclude mem init dynamic `if` from synthesis (Elliot Baptist) * [dv] Exclude some secded generation modules from coverage (Rupert Swarbrick) * [dv] Add a GUI debug mode (Martin Velay) * [dvsim] Improve error handling on slurm launcher (Robert Schilling) * [dvsim] Be a bit clearer about how modes get merged (Rupert Swarbrick) * [dvsim] Avoid comparing types in FlowCfg.py (Rupert Swarbrick) * [dvsim] Avoid comparing types in Deploy.py (Rupert Swarbrick) * [prim_pulse_sync] Add missing `include "prim_assert.sv"` (Andreas Kurth) * [dv, dvsim] Add job queue/lic wait timeout in addition to run timeout (Venkat Krishnan) * [dvsim] Remove unneeded check since exports are always defined (Robert Schilling) * [dvsim] Add slurm launcher (Robert Schilling) * [dv] Teach dv_base_reg to allow mubi regwen fields (Rupert Swarbrick) * [dv, dvsim] Update nc flag for interactive sim (Venkat Krishnan) * [dv, dvsim] Use file descriptors to share logfile across processes (Venkat Krishnan) * [dv, dvsim] remove support for post_cmd in nc run call (Venkat Krishnan) * [dv, dvsim] : Override NC node's TMPDIR with custom value (Venkat Krishnan) * [dv, dvsim] stability fixes for the nc job scheduler (Venkat Krishnan) * [prim,fpga] Add FPGA-specific primitive implementations for prim_xnor2 (Pirmin Vogel) * [prim] Remove prim_clock_gp_mux2 (Rupert Swarbrick) * [dv,vcs] Tidy up the comments where we disable coverage in a prim (Rupert Swarbrick) * [csr_utils_pkg,dv] Avoid bug on reset in csr_spinwait (Rupert Swarbrick) * [fpv,prim] Fix AlertPingOk_A in prim_alert_rxtx_async_assert_fpv (Rupert Swarbrick) * [prim,fpv] Fix AlertCheck0_A in prim_alert_rxtx_async_assert_fpv (Rupert Swarbrick) * [fpv,prim] Factor out FSM exprs in prim_alert_rxtx_async_assert_fpv (Rupert Swarbrick) * [prim,fpv] Increase timeouts in prim_alert_rxtx_async_assert_fpv (Rupert Swarbrick) * [prim,fpv] Fix bind statements in prim_alert_rxtx_async*_bind_fpv (Rupert Swarbrick) * fix job status poll logic when timeout is not specified (venkatk-ot) * Added support for another job scheduler. (Venkat Krishnan) * [ci, sival] Make testplan validator need bazel if si_stage != NA (Alex Jones) * [ci, sival] Create a validator for the testplans (Douglas Reis) * [python] remove pkg_resources usage (Gary Guo) * [prim,fpv] Remove initialisation before a test (Rupert Swarbrick) * [ascon, prim_ascon_duplex] add/connect error register (Michael Tempelmeier) * [ascon, prim_ascon_duplex] change no_ad and no_msg to mubi4 (Michael Tempelmeier) * [ascon, prim_ascon_duplex] add FSM State Output and connect to debug reg. (Michael Tempelmeier) * [dv] Avoid so many copies of count in csr_spinwait (Rupert Swarbrick) * [dv] Add some comments to csr_spinwait (Rupert Swarbrick) * [dv] Remove pre_reset_dly_clks argument from clk_rst_if.apply_reset (Rupert Swarbrick) * [prim,fpv] Fix the bind statement in prim_alert_rxtx_fatal_bind_fpv (Rupert Swarbrick) * [prim,fpv] Fix hierarchical names in prim_alert_rxtx_assert_fpv (Rupert Swarbrick) * [prim,fpv] Fix the bind statement in prim_alert_rxtx_bind_fpv (Rupert Swarbrick) * [prim,fpv] Get rid of ASSERT_KNOWN in an FPV context (Rupert Swarbrick) * [prim,fpv] Fix reset check in prim_esc_rxtx_assert_fpv (Rupert Swarbrick) * [prim,fpv] Fix hierarchical names in prim_esc_rxtx_assert_fpv (Rupert Swarbrick) * [prim,fpv] Fix binding in prim_esc_rxtx_fpv (Rupert Swarbrick) * [prim,fpv] Tweak DataKnown_A assertion in prim_fifo_sync.sv (Rupert Swarbrick) * [prim,fpv] Strengthen CntErrReported_A assertion in prim_count.sv (Rupert Swarbrick) * [dv,vcs] Tidy up how coverage is collected in assertion modules (Rupert Swarbrick) * [top_earlgrey] Reduce number of PRINCE half rounds for main SRAM (Pirmin Vogel) * [mem_bkdr_util] Support varying No. of PRINCE half rounds for scrambling (Pirmin Vogel) * [ascon, prim_ascon_duplex] fix MuBi coding style (Michael Tempelmeier) * [prim_ascon_duplex] fix asynchronous reset (Michael Tempelmeier) * [ascon, prim_ascon] improv .core-files naming (Michael Tempelmeier) * [ascon] integrate prim_ascon_duplex into comportable ip (Michael Tempelmeier) * [prim,fpv] Fix delays in assertions of prim_fifo_async_sram_adapter (Rupert Swarbrick) * [prim,fpv] Explicitly delay wready_o assertions by a cycle (Rupert Swarbrick) * [dvsim] Speed up gsutil operations. (Miguel Osorio) * [prim_ascon_duplex] change to mux and ready/valid implementation (Michael Tempelmeier) * [prim_ascon_duplex] add TB for prim_ascon_duplex (Michael Tempelmeier) * [prim_ascon_duplex] add ascon duplex prim (Michael Tempelmeier) * [bazel] Update rules_python to upstream 0.34.0 (James Wainwright) * [tools,vcs] Fix compilation warnings (Guillermo Maturana) * [dv] Allow assertions from ASSERT_FPV_LINEAR_FSM to complete (Rupert Swarbrick) * [prim_ascon] add testbench for ascon round function (Michael Tempelmeier) * [prim_ascon_sbox] add verilator-rule to prevent false UNOPTFLAT warnings (Michael Tempelmeier) * [prim_ascon] add unmasked ascon sbox and round function (Michael Tempelmeier) * [prim_ascon] add dpi model (Michael Tempelmeier) * Add vendor code from ascon/ascon-c@46f35c0 (Michael Tempelmeier) * [dv] Manually apply specialisation for mubi32_cov (Rupert Swarbrick) * [top_earlgrey,cdc] Transition to MeridianCDC (Andreas Kurth) * Revert "[dv] Add a quick exit in csr_rd_sub when in reset" (Rupert Swarbrick) * [util] Get rid of "type" field in Modes (Rupert Swarbrick) * [prim_esc_receiver] Register esc_req_o to avoid potential CDC issues (Pirmin Vogel) * [prim_count] Register err_o to avoid potential CDC issues downstream (Pirmin Vogel) * [dv] Add a quick exit in csr_rd_sub when in reset (Rupert Swarbrick) * [dv] Tidy up how reset lengths get calculated (Rupert Swarbrick) * [dv] Add writes_ignore_errors flag to reggen / dv_base_reg (Rupert Swarbrick) * [dv, csr_spinwait] debug printout (Antonio Martinez Zambrana) * [dv] update the ROM self hash GLS test (Tim Trippel) * [pinmux] Remove scan clocks from wakeup detector inputs (Alexander Williams) * [dvsim] Correctly handle fixed-seed=0 (Rupert Swarbrick) * [dv,chip_level] Fix chip_sw_lc_ctrl_program_error (Guillermo Maturana) * [dv] Improve debug prints from register aliasing sequence (Rupert Swarbrick) * [prim/lint] Move AscentLint waiver rules for prim_gf_mult into own file (Pirmin Vogel) * [top, rom_ctrl] Add missing TEST port for ROM macro (Pirmin Vogel) * [prim] Waive AscentLint errors inside prim_generic_pad_wrapper (Pirmin Vogel) * [dvsim] Get rid of unnecessary find_and_merge_modes function (Rupert Swarbrick) * [dvsim] Tweak find_and_merge_modes to be simpler to understand (Rupert Swarbrick) * [prim] Update AscentLint waiver file for prim_generic_clock_div (Pirmin Vogel) * [prim] Update lint waiver rule for prim_lfsr.sv (Pirmin Vogel) * [lint] Waive USE_BEFORE_DECL AscentLint errors for SV functions (Pirmin Vogel) * [prim] Waive SAME_NAME_TYPE AscentLint error (Pirmin Vogel) * [dv] Fix info message in csr_seq_lib.sv (Rupert Swarbrick) * [dv] Expand documentation comments about gaps in bit_bash_seq (Rupert Swarbrick) * [dv] Change a variable name in bash_register task (Rupert Swarbrick) * [dv] Add a default to a case statement in the bash_register task (Rupert Swarbrick) * [dv] Factor out part of task in csr_bit_bash_seq (Rupert Swarbrick) * [dv] Expand documentation comment above bash_kth_bit task (Rupert Swarbrick) * [prim] Waive lint warnings and errors in prim_[generic_]_flop_2sync (Pirmin Vogel) * [dv] Fix typo in prints in push_pull_monitor (Rupert Swarbrick) * [top_earlgrey,prim_ram_*_pkg] Connect memory test port (Andreas Kurth) * [prim/rtl] Allow for tech-specific impls of `prim_flop_2sync` (Andreas Kurth) * [dv] Fix ROM e2e JTAG tests. (Miguel Osorio) * [hmac,rtl/dv] DV synchronization and error handling fixes (Ghada Dessouky) * [kmac,prim_sha2/rtl] Fix lint error in `conv_endian32` (Andreas Kurth) * [kmac,prim_sha2/rtl] Remove unused `conv_endian64` function (Andreas Kurth) * [prim,fpv] Avoid warning message from Jasper with ASSERT_AT_RESET (Rupert Swarbrick) Signed-off-by: Samuel Riedel <[email protected]>
… constant Try like this for now. I have the feeling that the clock gate could just be removed, since it's anyway only instantiating a tech specific cell, which can also directly come form the fusesoc mapping
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Update the
vendor/lowrisc_ipdirectory to align Ibex with the latest version of the prims and fusesoc 2.4.3. The current prims were vendored in almost 1.5 years ago.This PR is currently a work in progress and will require cleanup before merging.
fusesocto align with OpenTitan's versiondv/uvm/core_ibex/common/primcan be removed entirelydv/uvm/core_ibex/ibex_dv.f)