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[RISCV] Bump Pointer Masking extension version #96715

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Merged
merged 4 commits into from
Jun 27, 2024
Merged

[RISCV] Bump Pointer Masking extension version #96715

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f6a4cf6
[RISCV] Bump Pointer Masking extension version
michaelmaitland Jun 25, 2024
97362ca
fixup! use versioned link
michaelmaitland Jun 26, 2024
c2ee30e
fixup! update clang/test/Preprocessor/riscv-target-features.c
michaelmaitland Jun 26, 2024
f9f4126
fixup! update line in ReleaseNotes.rst
michaelmaitland Jun 26, 2024
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2 changes: 1 addition & 1 deletion llvm/docs/RISCVUsage.rst
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Expand Up @@ -263,7 +263,7 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.

``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
LLVM implements the `v0.8.1 draft specification <https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf>`__.
LLVM implements the `v1.0.0-rc2 specification <https://github.com/riscv/riscv-j-extension/blob/master/zjpm-spec.pdf>`__.
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@topperc topperc Jun 25, 2024 •
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Please use the versioned link here https://github.com/riscv/riscv-j-extension/releases rather than master copy that will change with every update.


``experimental-ssqosid``
LLVM implements assembler support for the `v1.0-rc1 draft specification <https://github.com/riscv/riscv-ssqosid/releases/tag/v1.0-rc1>`_.
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1 change: 1 addition & 0 deletions llvm/docs/ReleaseNotes.rst
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Expand Up @@ -184,6 +184,7 @@ Changes to the RISC-V Backend
* B (the collection of the Zba, Zbb, Zbs extensions) is supported.
* Added smcdeleg, ssccfg, smcsrind, and sscsrind extensions to -march.
* ``-mcpu=syntacore-scr3-rv32`` and ``-mcpu=syntacore-scr3-rv64`` were added.
* Ssnpm, Smnpm, Smmpm, Sspm, and Supm are bumped to version 1.0.0

Changes to the WebAssembly Backend
----------------------------------
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10 changes: 5 additions & 5 deletions llvm/lib/Target/RISCV/RISCVFeatures.td
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Expand Up @@ -961,32 +961,32 @@ def FeatureStdExtSvpbmt
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
// present.
def FeatureStdExtSsnpm
: RISCVExperimentalExtension<"ssnpm", 0, 8,
: RISCVExperimentalExtension<"ssnpm", 1, 0,
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;

// A machine-level extension that provides pointer masking for the next lower
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
def FeatureStdExtSmnpm
: RISCVExperimentalExtension<"smnpm", 0, 8,
: RISCVExperimentalExtension<"smnpm", 1, 0,
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;

// A machine-level extension that provides pointer masking for M-mode.
def FeatureStdExtSmmpm
: RISCVExperimentalExtension<"smmpm", 0, 8,
: RISCVExperimentalExtension<"smmpm", 1, 0,
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;

// An extension that indicates that there is pointer-masking support available
// in supervisor mode, with some facility provided in the supervisor execution
// environment to control pointer masking.
def FeatureStdExtSspm
: RISCVExperimentalExtension<"sspm", 0, 8,
: RISCVExperimentalExtension<"sspm", 1, 0,
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;

// An extension that indicates that there is pointer-masking support available
// in user mode, with some facility provided in the application execution
// environment to control pointer masking.
def FeatureStdExtSupm
: RISCVExperimentalExtension<"supm", 0, 8,
: RISCVExperimentalExtension<"supm", 1, 0,
"'Supm' (Indicates User-mode Pointer Masking)">;

//===----------------------------------------------------------------------===//
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22 changes: 11 additions & 11 deletions llvm/test/CodeGen/RISCV/attributes.ll
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Expand Up @@ -406,11 +406,11 @@
; RV32ZAMA16B: .attribute 5, "rv32i2p1_zama16b1p0"
; RV32ZICFILP: .attribute 5, "rv32i2p1_zicfilp0p4_zicsr2p0"
; RV32ZABHA: .attribute 5, "rv32i2p1_a2p1_zabha1p0"
; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm0p8"
; RV32SMNPM: .attribute 5, "rv32i2p1_smnpm0p8"
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8"
; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8"
; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8"
; RV32SSNPM: .attribute 5, "rv32i2p1_ssnpm1p0"
; RV32SMNPM: .attribute 5, "rv32i2p1_smnpm1p0"
; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm1p0"
; RV32SSPM: .attribute 5, "rv32i2p1_sspm1p0"
; RV32SUPM: .attribute 5, "rv32i2p1_supm1p0"
; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0"

; RV64M: .attribute 5, "rv64i2p1_m2p0_zmmul1p0"
Expand Down Expand Up @@ -542,11 +542,11 @@
; RV64ZALASR: .attribute 5, "rv64i2p1_zalasr0p1"
; RV64ZICFILP: .attribute 5, "rv64i2p1_zicfilp0p4_zicsr2p0"
; RV64ZABHA: .attribute 5, "rv64i2p1_a2p1_zabha1p0"
; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm0p8"
; RV64SMNPM: .attribute 5, "rv64i2p1_smnpm0p8"
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8"
; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8"
; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8"
; RV64SSNPM: .attribute 5, "rv64i2p1_ssnpm1p0"
; RV64SMNPM: .attribute 5, "rv64i2p1_smnpm1p0"
; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm1p0"
; RV64SSPM: .attribute 5, "rv64i2p1_sspm1p0"
; RV64SUPM: .attribute 5, "rv64i2p1_supm1p0"
; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0"

; RVI20U32: .attribute 5, "rv32i2p1"
Expand All @@ -556,7 +556,7 @@
; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_zmmul1p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0"
; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm1p0_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0"
; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_zmmul1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0"
; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zmmul1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0"
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40 changes: 20 additions & 20 deletions llvm/test/MC/RISCV/attribute-arch.s
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Expand Up @@ -417,32 +417,32 @@
.attribute arch, "rv64i_xsfvfwmaccqqq"
# CHECK: attribute 5, "rv64i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0"

.attribute arch, "rv32i_ssnpm0p8"
# CHECK: attribute 5, "rv32i2p1_ssnpm0p8"
.attribute arch, "rv32i_ssnpm1p0"
# CHECK: attribute 5, "rv32i2p1_ssnpm1p0"

.attribute arch, "rv32i_smnpm0p8"
# CHECK: attribute 5, "rv32i2p1_smnpm0p8"
.attribute arch, "rv32i_smnpm1p0"
# CHECK: attribute 5, "rv32i2p1_smnpm1p0"

.attribute arch, "rv32i_smmpm0p8"
# CHECK: attribute 5, "rv32i2p1_smmpm0p8"
.attribute arch, "rv32i_smmpm1p0"
# CHECK: attribute 5, "rv32i2p1_smmpm1p0"

.attribute arch, "rv32i_sspm0p8"
# CHECK: attribute 5, "rv32i2p1_sspm0p8"
.attribute arch, "rv32i_sspm1p0"
# CHECK: attribute 5, "rv32i2p1_sspm1p0"

.attribute arch, "rv32i_supm0p8"
# CHECK: attribute 5, "rv32i2p1_supm0p8"
.attribute arch, "rv32i_supm1p0"
# CHECK: attribute 5, "rv32i2p1_supm1p0"

.attribute arch, "rv64i_ssnpm0p8"
# CHECK: attribute 5, "rv64i2p1_ssnpm0p8"
.attribute arch, "rv64i_ssnpm1p0"
# CHECK: attribute 5, "rv64i2p1_ssnpm1p0"

.attribute arch, "rv64i_smnpm0p8"
# CHECK: attribute 5, "rv64i2p1_smnpm0p8"
.attribute arch, "rv64i_smnpm1p0"
# CHECK: attribute 5, "rv64i2p1_smnpm1p0"

.attribute arch, "rv64i_smmpm0p8"
# CHECK: attribute 5, "rv64i2p1_smmpm0p8"
.attribute arch, "rv64i_smmpm1p0"
# CHECK: attribute 5, "rv64i2p1_smmpm1p0"

.attribute arch, "rv64i_sspm0p8"
# CHECK: attribute 5, "rv64i2p1_sspm0p8"
.attribute arch, "rv64i_sspm1p0"
# CHECK: attribute 5, "rv64i2p1_sspm1p0"

.attribute arch, "rv64i_supm0p8"
# CHECK: attribute 5, "rv64i2p1_supm0p8"
.attribute arch, "rv64i_supm1p0"
# CHECK: attribute 5, "rv64i2p1_supm1p0"
10 changes: 5 additions & 5 deletions llvm/unittests/TargetParser/RISCVISAInfoTest.cpp
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Expand Up @@ -1077,12 +1077,12 @@ Experimental extensions
ztso 0.1
zvfbfmin 1.0
zvfbfwma 1.0
smmpm 0.8
smnpm 0.8
ssnpm 0.8
sspm 0.8
smmpm 1.0
smnpm 1.0
ssnpm 1.0
sspm 1.0
ssqosid 1.0
supm 0.8
supm 1.0

Supported Profiles
rva20s64
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