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AMDGPU: Do not assert on v6x16 buffer load intrinsics #94966

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Merged
arsenm merged 1 commit into from
Jun 10, 2024
Merged

AMDGPU: Do not assert on v6x16 buffer load intrinsics #94966

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6 changes: 4 additions & 2 deletions llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -42,8 +42,10 @@ EVT AMDGPUTargetLowering::getEquivalentMemType(LLVMContext &Ctx, EVT VT) {
if (StoreSize <= 32)
return EVT::getIntegerVT(Ctx, StoreSize);

assert(StoreSize % 32 == 0 && "Store size not a multiple of 32");
return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);
if (StoreSize % 32 == 0)
return EVT::getVectorVT(Ctx, MVT::i32, StoreSize / 32);

return VT;
}

unsigned AMDGPUTargetLowering::numBitsUnsigned(SDValue Op, SelectionDAG &DAG) {
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8 changes: 8 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.bf16.xfail.ll
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@@ -0,0 +1,8 @@
; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=null %s 2>&1 | FileCheck %s

; CHECK: LLVM ERROR: Do not know how to widen the result of this operator!

define <6 x bfloat> @raw_ptr_buffer_load_v6bf16(ptr addrspace(8) inreg %rsrc) {
%val = call <6 x bfloat> @llvm.amdgcn.raw.ptr.buffer.load.v6bf16(ptr addrspace(8) %rsrc, i32 0, i32 0, i32 0)
ret <6 x bfloat> %val
}
11 changes: 11 additions & 0 deletions llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.store.bf16.xfail.ll
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@@ -0,0 +1,11 @@
; RUN: not --crash llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -filetype=null %s 2>&1 | FileCheck %s

; FIXME: This should be handled

; CHECK: LLVM ERROR: Do not know how to widen this operator's operand!


define void @buffer_store_v6bf16(ptr addrspace(8) inreg %rsrc, <6 x bfloat> %data, i32 %offset) {
call void @llvm.amdgcn.raw.ptr.buffer.store.v6bf16(<6 x bfloat> %data, ptr addrspace(8) %rsrc, i32 %offset, i32 0, i32 0)
ret void
}