[RISCV] Add processor definition for SpacemiT-X60

clang/test/Driver/riscv-cpus.c

@@ -31,6 +31,27 @@
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-feature" "+zks" "-target-feature" "+zksed" "-target-feature" "+zksh" "-target-feature" "+svinval"
 // MCPU-XIANGSHAN-NANHU-SAME: "-target-abi" "lp64d"
 
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=spacemit-x60 | FileCheck -check-prefix=MCPU-SPACEMIT-X60 %s
+// MCPU-SPACEMIT-X60: "-nostdsysteminc" "-target-cpu" "spacemit-x60"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+m" "-target-feature" "+a" "-target-feature" "+f" "-target-feature" "+d"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+c" "-target-feature" "+v" "-target-feature" "+zic64b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicbom" "-target-feature" "+zicbop" "-target-feature" "+zicboz"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccamoa" "-target-feature" "+ziccif" "-target-feature" "+zicclsm"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+ziccrse" "-target-feature" "+zicntr" "-target-feature" "+zicond"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zicsr" "-target-feature" "+zifencei" "-target-feature" "+zihintpause"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zihpm" "-target-feature" "+zmmul" "-target-feature" "+za64rs"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zfh" "-target-feature" "+zfhmin" "-target-feature" "+zba"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbb" "-target-feature" "+zbc" "-target-feature" "+zbkc"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zbs" "-target-feature" "+zkt" "-target-feature" "+zve32f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve32x" "-target-feature" "+zve64d" "-target-feature" "+zve64f"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zve64x" "-target-feature" "+zvfh" "-target-feature" "+zvfhmin"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl128b" "-target-feature" "+zvl256b" "-target-feature" "+zvl32b"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+zvl64b" "-target-feature" "+ssccptr" "-target-feature" "+sscounterenw"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+sstvala" "-target-feature" "+sstvecd" "-target-feature" "+svade"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svbare" "-target-feature" "+svinval" "-target-feature" "+svnapot"
+// MCPU-SPACEMIT-X60-SAME: "-target-feature" "+svpbmt"
+// MCPU-SPACEMIT-X60-SAME: "-target-abi" "lp64d"
+
 // We cannot check much for -mcpu=native, but it should be replaced by a valid CPU string.
 // RUN: %clang --target=riscv64 -### -c %s -mcpu=native 2> %t.err || true
 // RUN: FileCheck --input-file=%t.err -check-prefix=MCPU-NATIVE %s

clang/test/Misc/target-invalid-cpu-note.c

@@ -85,12 +85,12 @@
 
 // RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
 // RISCV64: error: unknown target CPU 'not-a-cpu'
-// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu{{$}}
+// RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu{{$}}
 
 // RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
 // TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
 // TUNE-RISCV32-NEXT: note: valid target CPU values are: generic-rv32, rocket-rv32, sifive-e20, sifive-e21, sifive-e24, sifive-e31, sifive-e34, sifive-e76, syntacore-scr1-base, syntacore-scr1-max, generic, rocket, sifive-7-series{{$}}
 
 // RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
 // TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
-// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}
+// TUNE-RISCV64-NEXT: note: valid target CPU values are: generic-rv64, rocket-rv64, sifive-p450, sifive-p670, sifive-s21, sifive-s51, sifive-s54, sifive-s76, sifive-u54, sifive-u74, sifive-x280, spacemit-x60, veyron-v1, xiangshan-nanhu, generic, rocket, sifive-7-series{{$}}

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -381,3 +381,20 @@ def XIANGSHAN_NANHU : RISCVProcessorModel<"xiangshan-nanhu",
                                             TuneZExtHFusion,
                                             TuneZExtWFusion,
                                             TuneShiftedZExtWFusion]>;
+
+def SPACEMIT_X60 : RISCVProcessorModel<"spacemit-x60",
+                                       NoSchedModel,
+                                       !listconcat(RVA22S64Features,
+                                       [FeatureStdExtV,
+                                        FeatureStdExtSvnapot,
+                                        FeatureStdExtZbc,
+                                        FeatureStdExtZbkc,
+                                        FeatureStdExtZfh,
+                                        FeatureStdExtZicond,
+                                        FeatureStdExtZmmul,
+                                        FeatureStdExtZvfh,
+                                        FeatureStdExtZvfhmin,
+                                        FeatureStdExtZvl32b,
+                                        FeatureStdExtZvl64b,
+                                        FeatureStdExtZvl128b,
+                                        FeatureStdExtZvl256b])>;