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[DAGCombine] Fix type mismatch in (shl X, cttz(Y)) -> (mul (Y & -Y), X) #94008

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Merged
dtcxzyw merged 2 commits into from
Jun 1, 2024
Merged

[DAGCombine] Fix type mismatch in (shl X, cttz(Y)) -> (mul (Y & -Y), X) #94008

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[DAGCombine] Fix type mismatch in `(shl X, cttz(Y)) -> (mul (Y & -Y),…
dtcxzyw May 31, 2024
b6faa33
[SDAG] Address review comments. NFC.
dtcxzyw Jun 1, 2024
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11 changes: 7 additions & 4 deletions llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10109,13 +10109,16 @@ SDValue DAGCombiner::visitSHL(SDNode *N) {

// fold (shl X, cttz(Y)) -> (mul (Y & -Y), X) if cttz is unsupported on the
// target.
if ((N1.getOpcode() == ISD::CTTZ || N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
N1.hasOneUse() && !TLI.isOperationLegalOrCustom(ISD::CTTZ, VT) &&
if (((N1.getOpcode() == ISD::CTTZ &&
VT.getScalarSizeInBits() >= ShiftVT.getScalarSizeInBits()) ||
N1.getOpcode() == ISD::CTTZ_ZERO_UNDEF) &&
N1.hasOneUse() && !TLI.isOperationLegalOrCustom(ISD::CTTZ, ShiftVT) &&
TLI.isOperationLegalOrCustom(ISD::MUL, VT)) {
SDValue Y = N1.getOperand(0);
SDLoc DL(N);
SDValue NegY = DAG.getNegative(Y, DL, VT);
SDValue And = DAG.getNode(ISD::AND, DL, VT, Y, NegY);
SDValue NegY = DAG.getNegative(Y, DL, ShiftVT);
SDValue And =
DAG.getZExtOrTrunc(DAG.getNode(ISD::AND, DL, ShiftVT, Y, NegY), DL, VT);
return DAG.getNode(ISD::MUL, DL, VT, And, N0);
}

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45 changes: 45 additions & 0 deletions llvm/test/CodeGen/PowerPC/pr85066.ll
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@@ -0,0 +1,45 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=powerpc64le < %s | FileCheck %s

; Tests from pr85066
define i64 @test_shl_zext_cttz(i16 %x) {
; CHECK-LABEL: test_shl_zext_cttz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: oris 3, 3, 1
; CHECK-NEXT: neg 4, 3
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
entry:
%cttz = tail call i16 @llvm.cttz.i16(i16 %x, i1 false)
%zext = zext i16 %cttz to i64
%res = shl i64 1, %zext
ret i64 %res
}

define i64 @test_shl_zext_cttz_zero_is_poison(i16 %x) {
; CHECK-LABEL: test_shl_zext_cttz_zero_is_poison:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: neg 4, 3
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: clrldi 3, 3, 32
; CHECK-NEXT: blr
entry:
%cttz = tail call i16 @llvm.cttz.i16(i16 %x, i1 true)
%zext = zext i16 %cttz to i64
%res = shl i64 1, %zext
ret i64 %res
}

define i16 @test_shl_trunc_cttz(i32 %x) {
; CHECK-LABEL: test_shl_trunc_cttz:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: neg 4, 3
; CHECK-NEXT: and 3, 3, 4
; CHECK-NEXT: blr
entry:
%cttz = tail call i32 @llvm.cttz.i32(i32 %x, i1 false)
%trunc = trunc i32 %cttz to i16
%res = shl i16 1, %trunc
ret i16 %res
}