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[DAGCombine] Fix multi-use miscompile in load combine #81586

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Merged
merged 1 commit into from
Feb 13, 2024
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[DAGCombine] Fix multi-use miscompile in load combine #81586

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2 changes: 1 addition & 1 deletion llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -9252,7 +9252,7 @@ SDValue DAGCombiner::MatchLoadCombine(SDNode *N) {

// Transfer chain users from old loads to the new load.
for (LoadSDNode *L : Loads)
DAG.ReplaceAllUsesOfValueWith(SDValue(L, 1), SDValue(NewLoad.getNode(), 1));
DAG.makeEquivalentMemoryOrdering(L, NewLoad);

if (!NeedsBswap)
return NewLoad;
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3 changes: 1 addition & 2 deletions llvm/test/CodeGen/X86/load-combine.ll
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Expand Up @@ -1283,7 +1283,6 @@ define i32 @zext_load_i32_by_i8_bswap_shl_16(ptr %arg) {
ret i32 %tmp8
}

; FIXME: This is a miscompile.
define i32 @pr80911_vector_load_multiuse(ptr %ptr, ptr %clobber) nounwind {
; CHECK-LABEL: pr80911_vector_load_multiuse:
; CHECK: # %bb.0:
Expand All @@ -1299,9 +1298,9 @@ define i32 @pr80911_vector_load_multiuse(ptr %ptr, ptr %clobber) nounwind {
;
; CHECK64-LABEL: pr80911_vector_load_multiuse:
; CHECK64: # %bb.0:
; CHECK64-NEXT: movl (%rdi), %ecx
; CHECK64-NEXT: movzwl (%rdi), %eax
; CHECK64-NEXT: movl $0, (%rsi)
; CHECK64-NEXT: movl (%rdi), %ecx
; CHECK64-NEXT: movl %ecx, (%rdi)
; CHECK64-NEXT: retq
%load = load <4 x i8>, ptr %ptr, align 16
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