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[CodeGen] Increase NumVisited limit in TwoAddressInstructionPass to 64 #80627

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[CodeGen] Increase NumVisited limit in TwoAddressInstructionPass to 64 #80627

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4 changes: 2 additions & 2 deletions llvm/lib/CodeGen/TwoAddressInstructionPass.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -921,7 +921,7 @@ bool TwoAddressInstructionPass::rescheduleMIBelowKill(
// Debug or pseudo instructions cannot be counted against the limit.
if (OtherMI.isDebugOrPseudoInstr())
continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
if (NumVisited > 64)
return false;
++NumVisited;
if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
Expand Down Expand Up @@ -1094,7 +1094,7 @@ bool TwoAddressInstructionPass::rescheduleKillAboveMI(
// Debug or pseudo instructions cannot be counted against the limit.
if (OtherMI.isDebugOrPseudoInstr())
continue;
if (NumVisited > 10) // FIXME: Arbitrary limit to reduce compile time cost.
if (NumVisited > 64)
return false;
++NumVisited;
if (OtherMI.hasUnmodeledSideEffects() || OtherMI.isCall() ||
Expand Down
200 changes: 92 additions & 108 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-extends.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -236,22 +236,20 @@ define void @sext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
; CHECK-NEXT: sunpklo z4.d, z2.s
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: mov z7.d, z1.d
; CHECK-NEXT: sunpklo z2.d, z2.s
; CHECK-NEXT: sunpklo z7.d, z1.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: sunpklo z5.d, z3.s
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8
; CHECK-NEXT: sunpklo z2.d, z2.s
; CHECK-NEXT: sunpklo z1.d, z1.s
; CHECK-NEXT: mov z6.d, z0.d
; CHECK-NEXT: sunpklo z6.d, z0.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: sunpklo z3.d, z3.s
; CHECK-NEXT: stp q4, q2, [x0]
; CHECK-NEXT: sunpklo z4.d, z7.s
; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8
; CHECK-NEXT: sunpklo z0.d, z0.s
; CHECK-NEXT: stp q7, q1, [x0, #32]
; CHECK-NEXT: stp q5, q3, [x0, #64]
; CHECK-NEXT: sunpklo z2.d, z6.s
; CHECK-NEXT: stp q1, q4, [x0, #32]
; CHECK-NEXT: stp q0, q2, [x0, #96]
; CHECK-NEXT: stp q6, q0, [x0, #96]
; CHECK-NEXT: ret
%b = sext <16 x i8> %a to <16 x i64>
store <16 x i64> %b, ptr %out
Expand All @@ -263,63 +261,57 @@ define void @sext_v32i8_v32i64(ptr %in, ptr %out) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
; CHECK-NEXT: add z0.b, z0.b, z0.b
; CHECK-NEXT: add z1.b, z1.b, z1.b
; CHECK-NEXT: mov z2.d, z0.d
; CHECK-NEXT: sunpklo z0.h, z0.b
; CHECK-NEXT: mov z3.d, z1.d
; CHECK-NEXT: sunpklo z1.h, z1.b
; CHECK-NEXT: add z2.b, z1.b, z1.b
; CHECK-NEXT: sunpklo z3.h, z0.b
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: sunpklo z1.h, z2.b
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: sunpklo z0.h, z0.b
; CHECK-NEXT: sunpklo z4.s, z3.h
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: sunpklo z4.s, z0.h
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: sunpklo z5.s, z1.h
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: sunpklo z2.h, z2.b
; CHECK-NEXT: sunpklo z3.h, z3.b
; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: sunpklo z16.d, z4.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: sunpklo z6.s, z0.h
; CHECK-NEXT: sunpklo z3.s, z3.h
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: sunpklo z7.d, z4.s
; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8
; CHECK-NEXT: sunpklo z1.s, z1.h
; CHECK-NEXT: sunpklo z17.d, z5.s
; CHECK-NEXT: sunpklo z16.d, z5.s
; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8
; CHECK-NEXT: sunpklo z6.s, z2.h
; CHECK-NEXT: sunpklo z7.s, z3.h
; CHECK-NEXT: sunpklo z17.s, z2.h
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: sunpklo z4.d, z4.s
; CHECK-NEXT: sunpklo z1.s, z1.h
; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: sunpklo z18.d, z6.s
; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8
; CHECK-NEXT: sunpklo z19.d, z3.s
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: sunpklo z19.d, z0.s
; CHECK-NEXT: sunpklo z4.d, z4.s
; CHECK-NEXT: sunpklo z5.d, z5.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: sunpklo z2.s, z2.h
; CHECK-NEXT: sunpklo z18.d, z6.s
; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8
; CHECK-NEXT: sunpklo z3.s, z3.h
; CHECK-NEXT: stp q16, q4, [x1, #128]
; CHECK-NEXT: mov z16.d, z7.d
; CHECK-NEXT: sunpklo z0.d, z0.s
; CHECK-NEXT: stp q17, q5, [x1]
; CHECK-NEXT: sunpklo z5.d, z7.s
; CHECK-NEXT: sunpklo z4.d, z6.s
; CHECK-NEXT: mov z6.d, z1.d
; CHECK-NEXT: ext z16.b, z16.b, z7.b, #8
; CHECK-NEXT: mov z7.d, z2.d
; CHECK-NEXT: stp q19, q0, [x1, #160]
; CHECK-NEXT: sunpklo z0.d, z2.s
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
; CHECK-NEXT: sunpklo z1.d, z1.s
; CHECK-NEXT: stp q18, q4, [x1, #192]
; CHECK-NEXT: mov z4.d, z3.d
; CHECK-NEXT: ext z7.b, z7.b, z2.b, #8
; CHECK-NEXT: sunpklo z16.d, z16.s
; CHECK-NEXT: sunpklo z6.d, z6.s
; CHECK-NEXT: ext z4.b, z4.b, z3.b, #8
; CHECK-NEXT: sunpklo z2.d, z7.s
; CHECK-NEXT: sunpklo z3.d, z3.s
; CHECK-NEXT: stp q5, q16, [x1, #64]
; CHECK-NEXT: stp q1, q6, [x1, #32]
; CHECK-NEXT: sunpklo z1.d, z4.s
; CHECK-NEXT: stp q0, q2, [x1, #224]
; CHECK-NEXT: stp q3, q1, [x1, #96]
; CHECK-NEXT: stp q16, q5, [x1]
; CHECK-NEXT: sunpklo z5.d, z1.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: stp q7, q4, [x1, #128]
; CHECK-NEXT: sunpklo z4.d, z17.s
; CHECK-NEXT: ext z17.b, z17.b, z17.b, #8
; CHECK-NEXT: stp q18, q6, [x1, #192]
; CHECK-NEXT: sunpklo z6.d, z0.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: stp q19, q3, [x1, #160]
; CHECK-NEXT: sunpklo z3.d, z2.s
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: sunpklo z7.d, z17.s
; CHECK-NEXT: sunpklo z1.d, z1.s
; CHECK-NEXT: sunpklo z0.d, z0.s
; CHECK-NEXT: sunpklo z2.d, z2.s
; CHECK-NEXT: stp q5, q1, [x1, #32]
; CHECK-NEXT: stp q4, q7, [x1, #64]
; CHECK-NEXT: stp q3, q2, [x1, #96]
; CHECK-NEXT: stp q6, q0, [x1, #224]
; CHECK-NEXT: ret
%a = load <32 x i8>, ptr %in
%b = add <32 x i8> %a, %a
Expand Down Expand Up @@ -661,22 +653,20 @@ define void @zext_v16i8_v16i64(<16 x i8> %a, ptr %out) {
; CHECK-NEXT: uunpklo z4.d, z2.s
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: mov z7.d, z1.d
; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: uunpklo z7.d, z1.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: uunpklo z5.d, z3.s
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: ext z7.b, z7.b, z1.b, #8
; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: mov z6.d, z0.d
; CHECK-NEXT: uunpklo z6.d, z0.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: uunpklo z3.d, z3.s
; CHECK-NEXT: stp q4, q2, [x0]
; CHECK-NEXT: uunpklo z4.d, z7.s
; CHECK-NEXT: ext z6.b, z6.b, z0.b, #8
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: stp q7, q1, [x0, #32]
; CHECK-NEXT: stp q5, q3, [x0, #64]
; CHECK-NEXT: uunpklo z2.d, z6.s
; CHECK-NEXT: stp q1, q4, [x0, #32]
; CHECK-NEXT: stp q0, q2, [x0, #96]
; CHECK-NEXT: stp q6, q0, [x0, #96]
; CHECK-NEXT: ret
%b = zext <16 x i8> %a to <16 x i64>
store <16 x i64> %b, ptr %out
Expand All @@ -688,63 +678,57 @@ define void @zext_v32i8_v32i64(ptr %in, ptr %out) {
; CHECK: // %bb.0:
; CHECK-NEXT: ldp q1, q0, [x0]
; CHECK-NEXT: add z0.b, z0.b, z0.b
; CHECK-NEXT: add z1.b, z1.b, z1.b
; CHECK-NEXT: mov z2.d, z0.d
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: mov z3.d, z1.d
; CHECK-NEXT: uunpklo z1.h, z1.b
; CHECK-NEXT: add z2.b, z1.b, z1.b
; CHECK-NEXT: uunpklo z3.h, z0.b
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: uunpklo z1.h, z2.b
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: uunpklo z0.h, z0.b
; CHECK-NEXT: uunpklo z4.s, z3.h
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: uunpklo z4.s, z0.h
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: uunpklo z5.s, z1.h
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: uunpklo z2.h, z2.b
; CHECK-NEXT: uunpklo z3.h, z3.b
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z16.d, z4.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: uunpklo z6.s, z0.h
; CHECK-NEXT: uunpklo z3.s, z3.h
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: uunpklo z7.d, z4.s
; CHECK-NEXT: ext z4.b, z4.b, z4.b, #8
; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpklo z17.d, z5.s
; CHECK-NEXT: uunpklo z16.d, z5.s
; CHECK-NEXT: ext z5.b, z5.b, z5.b, #8
; CHECK-NEXT: uunpklo z6.s, z2.h
; CHECK-NEXT: uunpklo z7.s, z3.h
; CHECK-NEXT: uunpklo z17.s, z2.h
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: uunpklo z4.d, z4.s
; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z18.d, z6.s
; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8
; CHECK-NEXT: uunpklo z19.d, z3.s
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: uunpklo z19.d, z0.s
; CHECK-NEXT: uunpklo z4.d, z4.s
; CHECK-NEXT: uunpklo z5.d, z5.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: uunpklo z2.s, z2.h
; CHECK-NEXT: uunpklo z18.d, z6.s
; CHECK-NEXT: ext z6.b, z6.b, z6.b, #8
; CHECK-NEXT: uunpklo z3.s, z3.h
; CHECK-NEXT: stp q16, q4, [x1, #128]
; CHECK-NEXT: mov z16.d, z7.d
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: stp q17, q5, [x1]
; CHECK-NEXT: uunpklo z5.d, z7.s
; CHECK-NEXT: uunpklo z4.d, z6.s
; CHECK-NEXT: mov z6.d, z1.d
; CHECK-NEXT: ext z16.b, z16.b, z7.b, #8
; CHECK-NEXT: mov z7.d, z2.d
; CHECK-NEXT: stp q19, q0, [x1, #160]
; CHECK-NEXT: uunpklo z0.d, z2.s
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: stp q18, q4, [x1, #192]
; CHECK-NEXT: mov z4.d, z3.d
; CHECK-NEXT: ext z7.b, z7.b, z2.b, #8
; CHECK-NEXT: uunpklo z16.d, z16.s
; CHECK-NEXT: uunpklo z6.d, z6.s
; CHECK-NEXT: ext z4.b, z4.b, z3.b, #8
; CHECK-NEXT: uunpklo z2.d, z7.s
; CHECK-NEXT: uunpklo z3.d, z3.s
; CHECK-NEXT: stp q5, q16, [x1, #64]
; CHECK-NEXT: stp q1, q6, [x1, #32]
; CHECK-NEXT: uunpklo z1.d, z4.s
; CHECK-NEXT: stp q0, q2, [x1, #224]
; CHECK-NEXT: stp q3, q1, [x1, #96]
; CHECK-NEXT: stp q16, q5, [x1]
; CHECK-NEXT: uunpklo z5.d, z1.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: stp q7, q4, [x1, #128]
; CHECK-NEXT: uunpklo z4.d, z17.s
; CHECK-NEXT: ext z17.b, z17.b, z17.b, #8
; CHECK-NEXT: stp q18, q6, [x1, #192]
; CHECK-NEXT: uunpklo z6.d, z0.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: stp q19, q3, [x1, #160]
; CHECK-NEXT: uunpklo z3.d, z2.s
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: uunpklo z7.d, z17.s
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: stp q5, q1, [x1, #32]
; CHECK-NEXT: stp q4, q7, [x1, #64]
; CHECK-NEXT: stp q3, q2, [x1, #96]
; CHECK-NEXT: stp q6, q0, [x1, #224]
; CHECK-NEXT: ret
%a = load <32 x i8>, ptr %in
%b = add <32 x i8> %a, %a
Expand Down
78 changes: 34 additions & 44 deletions llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-to-fp.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -207,36 +207,31 @@ define void @ucvtf_v16i16_v16f64(ptr %a, ptr %b) {
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: uunpklo z0.s, z0.h
; CHECK-NEXT: uunpklo z1.s, z1.h
; CHECK-NEXT: mov z4.d, z2.d
; CHECK-NEXT: mov z7.d, z3.d
; CHECK-NEXT: mov z5.d, z0.d
; CHECK-NEXT: ext z4.b, z4.b, z2.b, #8
; CHECK-NEXT: uunpklo z4.d, z2.s
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: uunpklo z7.d, z3.s
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: uunpklo z5.d, z0.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: uunpklo z2.d, z2.s
; CHECK-NEXT: mov z6.d, z1.d
; CHECK-NEXT: ext z7.b, z7.b, z3.b, #8
; CHECK-NEXT: uunpklo z6.d, z1.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: uunpklo z3.d, z3.s
; CHECK-NEXT: ext z5.b, z5.b, z0.b, #8
; CHECK-NEXT: uunpklo z4.d, z4.s
; CHECK-NEXT: ucvtf z4.d, p0/m, z4.d
; CHECK-NEXT: uunpklo z0.d, z0.s
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
; CHECK-NEXT: uunpklo z1.d, z1.s
; CHECK-NEXT: ucvtf z2.d, p0/m, z2.d
; CHECK-NEXT: ucvtf z5.d, p0/m, z5.d
; CHECK-NEXT: ucvtf z6.d, p0/m, z6.d
; CHECK-NEXT: ucvtf z3.d, p0/m, z3.d
; CHECK-NEXT: uunpklo z7.d, z7.s
; CHECK-NEXT: uunpklo z5.d, z5.s
; CHECK-NEXT: ucvtf z4.d, p0/m, z4.d
; CHECK-NEXT: ucvtf z0.d, p0/m, z0.d
; CHECK-NEXT: uunpklo z6.d, z6.s
; CHECK-NEXT: ucvtf z1.d, p0/m, z1.d
; CHECK-NEXT: ucvtf z5.d, p0/m, z5.d
; CHECK-NEXT: stp q2, q4, [x1, #64]
; CHECK-NEXT: movprfx z2, z6
; CHECK-NEXT: ucvtf z2.d, p0/m, z6.d
; CHECK-NEXT: stp q1, q2, [x1, #32]
; CHECK-NEXT: stp q0, q5, [x1, #96]
; CHECK-NEXT: movprfx z0, z7
; CHECK-NEXT: ucvtf z0.d, p0/m, z7.d
; CHECK-NEXT: stp q3, q0, [x1]
; CHECK-NEXT: stp q4, q2, [x1, #64]
; CHECK-NEXT: movprfx z2, z7
; CHECK-NEXT: ucvtf z2.d, p0/m, z7.d
; CHECK-NEXT: stp q2, q3, [x1]
; CHECK-NEXT: stp q5, q0, [x1, #96]
; CHECK-NEXT: stp q6, q1, [x1, #32]
; CHECK-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%res = uitofp <16 x i16> %op1 to <16 x double>
Expand Down Expand Up @@ -780,36 +775,31 @@ define void @scvtf_v16i16_v16f64(ptr %a, ptr %b) {
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: sunpklo z0.s, z0.h
; CHECK-NEXT: sunpklo z1.s, z1.h
; CHECK-NEXT: mov z4.d, z2.d
; CHECK-NEXT: mov z7.d, z3.d
; CHECK-NEXT: mov z5.d, z0.d
; CHECK-NEXT: ext z4.b, z4.b, z2.b, #8
; CHECK-NEXT: sunpklo z4.d, z2.s
; CHECK-NEXT: ext z2.b, z2.b, z2.b, #8
; CHECK-NEXT: sunpklo z7.d, z3.s
; CHECK-NEXT: ext z3.b, z3.b, z3.b, #8
; CHECK-NEXT: sunpklo z5.d, z0.s
; CHECK-NEXT: ext z0.b, z0.b, z0.b, #8
; CHECK-NEXT: sunpklo z2.d, z2.s
; CHECK-NEXT: mov z6.d, z1.d
; CHECK-NEXT: ext z7.b, z7.b, z3.b, #8
; CHECK-NEXT: sunpklo z6.d, z1.s
; CHECK-NEXT: ext z1.b, z1.b, z1.b, #8
; CHECK-NEXT: sunpklo z3.d, z3.s
; CHECK-NEXT: ext z5.b, z5.b, z0.b, #8
; CHECK-NEXT: sunpklo z4.d, z4.s
; CHECK-NEXT: scvtf z4.d, p0/m, z4.d
; CHECK-NEXT: sunpklo z0.d, z0.s
; CHECK-NEXT: ext z6.b, z6.b, z1.b, #8
; CHECK-NEXT: sunpklo z1.d, z1.s
; CHECK-NEXT: scvtf z2.d, p0/m, z2.d
; CHECK-NEXT: scvtf z5.d, p0/m, z5.d
; CHECK-NEXT: scvtf z6.d, p0/m, z6.d
; CHECK-NEXT: scvtf z3.d, p0/m, z3.d
; CHECK-NEXT: sunpklo z7.d, z7.s
; CHECK-NEXT: sunpklo z5.d, z5.s
; CHECK-NEXT: scvtf z4.d, p0/m, z4.d
; CHECK-NEXT: scvtf z0.d, p0/m, z0.d
; CHECK-NEXT: sunpklo z6.d, z6.s
; CHECK-NEXT: scvtf z1.d, p0/m, z1.d
; CHECK-NEXT: scvtf z5.d, p0/m, z5.d
; CHECK-NEXT: stp q2, q4, [x1, #64]
; CHECK-NEXT: movprfx z2, z6
; CHECK-NEXT: scvtf z2.d, p0/m, z6.d
; CHECK-NEXT: stp q1, q2, [x1, #32]
; CHECK-NEXT: stp q0, q5, [x1, #96]
; CHECK-NEXT: movprfx z0, z7
; CHECK-NEXT: scvtf z0.d, p0/m, z7.d
; CHECK-NEXT: stp q3, q0, [x1]
; CHECK-NEXT: stp q4, q2, [x1, #64]
; CHECK-NEXT: movprfx z2, z7
; CHECK-NEXT: scvtf z2.d, p0/m, z7.d
; CHECK-NEXT: stp q2, q3, [x1]
; CHECK-NEXT: stp q5, q0, [x1, #96]
; CHECK-NEXT: stp q6, q1, [x1, #32]
; CHECK-NEXT: ret
%op1 = load <16 x i16>, ptr %a
%res = sitofp <16 x i16> %op1 to <16 x double>
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