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Merged
merged 19 commits into from
Jan 24, 2024
Merged

[AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/… #78414

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ef5080c
[AMDGPU][GFX12] VOP encoding and codegen - add support for v_cvt fp8/…
matejaMarjanovic Jan 15, 2024
a91e42a
Update tests
mariusz-sikora-at-amd Jan 17, 2024
01d8b5e
Merge main into masikora/gfx12-cvt-fp8
mariusz-sikora-at-amd Jan 18, 2024
8e058e0
Update feature naming to FP8ConversionInsts
mariusz-sikora-at-amd Jan 18, 2024
6149014
Update test
mariusz-sikora-at-amd Jan 18, 2024
4996c77
Move instruction closer to place where used
mariusz-sikora-at-amd Jan 18, 2024
a36de86
Don't use getMCReg
mariusz-sikora-at-amd Jan 18, 2024
afe32a9
Remove VOP1 suffix from function name
mariusz-sikora-at-amd Jan 18, 2024
685d767
Merge main into masikora/gfx12-cvt-fp8
mariusz-sikora-at-amd Jan 18, 2024
7de5e75
Add fp8-conversion-insts feature to clang
mariusz-sikora-at-amd Jan 19, 2024
9ad8493
Merge main into masikora/gfx12-cvt-fp8
mariusz-sikora-at-amd Jan 19, 2024
9a7989f
Merge main into masikora/gfx12-cvt-fp8
mariusz-sikora-at-amd Jan 22, 2024
3211bc3
Remove OP_SEL_1 from Cvt_F32_F8_Pat_OpSel pattern
mariusz-sikora-at-amd Jan 22, 2024
55d4d1b
Update handling op_sel by Mirko Brkušanin
mbrkusanin Jan 22, 2024
55d611a
Remove dummy operands by Mirko Brkušanin
mbrkusanin Jan 22, 2024
585e918
[AMDGPU] Properly check op_sel in GCNDPPCombine
mbrkusanin Jan 23, 2024
a3610b5
Merge main into masikora/gfx12-cvt-fp8
mariusz-sikora-at-amd Jan 23, 2024
1db3bf4
Update tests
mariusz-sikora-at-amd Jan 23, 2024
5270f1e
Merge main into masikora/gfx12-cvt-fp8
mariusz-sikora-at-amd Jan 24, 2024
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4 changes: 3 additions & 1 deletion llvm/lib/Target/AMDGPU/AMDGPU.td
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Original file line number Diff line number Diff line change
Expand Up @@ -1495,14 +1495,16 @@ def FeatureISAVersion12 : FeatureSet<
FeatureFlatAtomicFaddF32Inst,
FeatureImageInsts,
FeatureExtendedImageInsts,
FeatureFP8Insts,
FeaturePackedTID,
FeatureVcmpxPermlaneHazard,
FeatureSALUFloatInsts,
FeaturePseudoScalarTrans,
FeatureHasRestrictedSOffset,
FeatureVGPRSingleUseHintInsts,
FeatureMADIntraFwdBug,
FeatureScalarDwordx3Loads]>;
FeatureScalarDwordx3Loads,
FeatureDPPSrc1SGPR]>;

//===----------------------------------------------------------------------===//

Expand Down
68 changes: 66 additions & 2 deletions llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3500,6 +3500,9 @@ bool AMDGPUAsmParser::usesConstantBus(const MCInst &Inst, unsigned OpIdx) {
return !isInlineConstant(Inst, OpIdx);
} else if (MO.isReg()) {
auto Reg = MO.getReg();
if (!Reg) {
return false;
}
const MCRegisterInfo *TRI = getContext().getRegisterInfo();
auto PReg = mc2PseudoReg(Reg);
return isSGPR(PReg, TRI) && PReg != SGPR_NULL;
Expand Down Expand Up @@ -8273,6 +8276,16 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands,
((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
}

if (isVOP1Cvt_F32_Fp8_Bf8_e64(Opc) &&
Opc != AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 &&
Opc != AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I++]);
Op.addRegOrImmWithFPInputModsOperands(Inst, 1); // src0
// Add dummy src1
Inst.addOperand(MCOperand::createImm(0));
Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(0, getSTI())));
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@kosarev kosarev Jan 18, 2024

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Probably no need to call getMCReg() for NoRegister?

Are these dummy operands really necessary? By having them, we just seem to give ourselves more work handling them with custom code. NoRegister register operands look a bit weird.

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@mariusz-sikora-at-amd mariusz-sikora-at-amd Jan 18, 2024

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Yes, I think we can remove getMCReg(). I will change in other places also.

We will need these dummy operands when doing cvtVOP3P here:

llvm-project/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp

Line 8414 in 99cae9a

OpSel = Inst.getOperand(OpSelIdx).getImm();
. Without them we will crash on out-of-bound access.

}

for (unsigned E = Operands.size(); I != E; ++I) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
Expand Down Expand Up @@ -8321,12 +8334,20 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands,
const bool IsPacked = (Desc.TSFlags & SIInstrFlags::IsPacked) != 0;

if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_vi) {
Opc == AMDGPU::V_CVT_SR_FP8_F32_vi ||
Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_gfx12 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_gfx12) {
Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods
Inst.addOperand(Inst.getOperand(0));
}

if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {
// Adding vdst_in operand is already covered for these DPP instructions in
// cvtVOP3DPP.
if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in) &&
!(Opc == AMDGPU::V_CVT_PK_BF8_F32_e64_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_PK_FP8_F32_e64_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_PK_BF8_F32_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_PK_FP8_F32_e64_dpp8_gfx12)) {
assert(!IsPacked);
Inst.addOperand(Inst.getOperand(0));
}
Expand Down Expand Up @@ -8765,6 +8786,11 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
int OldIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old);
int Src2ModIdx =
AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src2_modifiers);
int VdstInIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in);
bool IsVOP3CvtSrDpp = Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12;
bool IsMAC = OldIdx != -1 && Src2ModIdx != -1 &&
Desc.getOperandConstraint(OldIdx, MCOI::TIED_TO) == -1;

Expand All @@ -8788,6 +8814,20 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
}
}

if (VdstInIdx != -1) {
int NumOperands = Inst.getNumOperands();
if (VdstInIdx == NumOperands)
Inst.addOperand(Inst.getOperand(0));
}

if (IsVOP3CvtSrDpp) {
int NumOperands = Inst.getNumOperands();
if (Src2ModIdx == NumOperands) {
Inst.addOperand(MCOperand::createImm(0));
Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(0, getSTI())));
}
}

auto TiedTo = Desc.getOperandConstraint(Inst.getNumOperands(),
MCOI::TIED_TO);
if (TiedTo != -1) {
Expand All @@ -8801,6 +8841,13 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands,
Fi = Op.getImm();
} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
Op.addRegOrImmWithFPInputModsOperands(Inst, 2);
if (isVOP1Cvt_F32_Fp8_Bf8_e64(Inst.getOpcode()) &&
Inst.getOpcode() != AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 &&
Inst.getOpcode() != AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12) {
// Add dummy src1
Inst.addOperand(MCOperand::createImm(0));
Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(0, getSTI())));
}
} else if (Op.isReg()) {
Op.addRegOperands(Inst, 1);
} else if (Op.isImm() &&
Expand Down Expand Up @@ -8847,6 +8894,7 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool I
OptionalImmIndexMap OptionalIdx;

unsigned I = 1;
const unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
Expand Down Expand Up @@ -8874,6 +8922,14 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool I
Op.addImmOperands(Inst, 1);
} else if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
Op.addRegWithFPInputModsOperands(Inst, 2);
if (Opc == AMDGPU::V_CVT_F32_BF8_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_F32_BF8_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_dpp8_gfx12) {
// Add dummy src1
Inst.addOperand(MCOperand::createImm(0));
Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(0, getSTI())));
}
} else if (Op.isDppFI()) {
Fi = Op.getImm();
} else if (Op.isReg()) {
Expand All @@ -8884,6 +8940,14 @@ void AMDGPUAsmParser::cvtDPP(MCInst &Inst, const OperandVector &Operands, bool I
} else {
if (isRegOrImmWithInputMods(Desc, Inst.getNumOperands())) {
Op.addRegWithFPInputModsOperands(Inst, 2);
if (Opc == AMDGPU::V_CVT_F32_BF8_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_F32_BF8_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_dpp8_gfx12) {
// Add dummy src1
Inst.addOperand(MCOperand::createImm(0));
Inst.addOperand(MCOperand::createReg(AMDGPU::getMCReg(0, getSTI())));
}
} else if (Op.isReg()) {
Op.addRegOperands(Inst, 1);
} else if (Op.isDPPCtrl()) {
Expand Down
50 changes: 49 additions & 1 deletion llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -522,6 +522,15 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
convertVOPCDPPInst(MI); // Special VOP3 case
} else {
assert(MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::VOP3);

if (AMDGPU::isVOP1Cvt_F32_Fp8_Bf8_e64(MI.getOpcode())) {
// Add omod and clamp modifiers.
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::omod);
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::clamp);
}

convertVOP3DPPInst(MI); // Regular VOP3 case
}
};
Expand Down Expand Up @@ -691,8 +700,15 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,

Res = tryDecodeInst(DecoderTableGFX1264, DecoderTableGFX12_FAKE1664, MI, QW,
Address, CS);
if (Res)
if (Res) {
if (AMDGPU::isVOP1Cvt_F32_Fp8_Bf8_e64(MI.getOpcode())) {
// Add omod and clamp modifiers.
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::clamp);
}
break;
}

Res = tryDecodeInst(DecoderTableGFX1164, DecoderTableGFX11_FAKE1664, MI, QW,
Address, CS);
Expand All @@ -708,6 +724,13 @@ DecodeStatus AMDGPUDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
AMDGPU::OpName::src2_modifiers);
}

if (Res && (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp ||
MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp)) {
// Insert dummy unused src2_modifiers.
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::src2_modifiers);
}

if (Res && (MCII->get(MI.getOpcode()).TSFlags & SIInstrFlags::DS) &&
!AMDGPU::hasGDS(STI)) {
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::gds);
Expand Down Expand Up @@ -938,6 +961,13 @@ void AMDGPUDisassembler::convertMacDPPInst(MCInst &MI) const {
// first add optional MI operands to check FI
DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
unsigned Opc = MI.getOpcode();

if (AMDGPU::isVOP1Cvt_F32_Fp8_Bf8_e64(Opc)) {
// Add omod and clamp modifiers.
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::omod);
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
}

if (MCII->get(Opc).TSFlags & SIInstrFlags::VOP3P) {
convertVOP3PDPPInst(MI);
} else if ((MCII->get(Opc).TSFlags & SIInstrFlags::VOPC) ||
Expand All @@ -947,6 +977,15 @@ DecodeStatus AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const {
if (isMacDPP(MI))
convertMacDPPInst(MI);

int VDstInIdx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);
if (VDstInIdx != -1)
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in);

if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 ||
MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12)
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2);

unsigned DescNumOps = MCII->get(Opc).getNumOperands();
if (MI.getNumOperands() < DescNumOps &&
AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
Expand All @@ -973,6 +1012,15 @@ DecodeStatus AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const {
if (isMacDPP(MI))
convertMacDPPInst(MI);

int VDstInIdx =
AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::vdst_in);
if (VDstInIdx != -1)
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in);

if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 ||
MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12)
insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2);

unsigned Opc = MI.getOpcode();
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
if (MI.getNumOperands() < DescNumOps &&
Expand Down
4 changes: 3 additions & 1 deletion llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -1300,7 +1300,9 @@ void AMDGPUInstPrinter::printOpSel(const MCInst *MI, unsigned,
const MCSubtargetInfo &STI,
raw_ostream &O) {
unsigned Opc = MI->getOpcode();
if (isPermlane16(Opc)) {
if (isPermlane16(Opc) || (isVOP1Cvt_F32_Fp8_Bf8_e64(Opc) &&
Opc != AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 &&
Opc != AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12)) {
auto FIN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers);
auto BCN = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers);
unsigned FI = !!(MI->getOperand(FIN).getImm() & SISrcMods::OP_SEL_0);
Expand Down
11 changes: 11 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -503,6 +503,17 @@ bool isPermlane16(unsigned Opc) {
Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
}

bool isVOP1Cvt_F32_Fp8_Bf8_e64(unsigned Opc) {
return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
Opc == AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 ||
Opc == AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12;
}

bool isGenericAtomic(unsigned Opc) {
return Opc == AMDGPU::G_AMDGPU_ATOMIC_FMIN ||
Opc == AMDGPU::G_AMDGPU_ATOMIC_FMAX ||
Expand Down
3 changes: 3 additions & 0 deletions llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h
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Original file line number Diff line number Diff line change
Expand Up @@ -542,6 +542,9 @@ bool isPermlane16(unsigned Opc);
LLVM_READNONE
bool isGenericAtomic(unsigned Opc);

LLVM_READNONE
bool isVOP1Cvt_F32_Fp8_Bf8_e64(unsigned Opc);

namespace VOPD {

enum Component : unsigned {
Expand Down
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