Skip to content

[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB #74114

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
jiahanxie353 merged 12 commits into from
Feb 1, 2024

clang format off to put PartMappings in single lines

5d60e8d
Select commit
Loading
Failed to load commit list.
Merged

[RISCV][GISel] RegBank select and instruction select for vector G_ADD, G_SUB #74114

clang format off to put PartMappings in single lines
5d60e8d
Select commit
Loading
Failed to load commit list.

Workflow runs completed with no jobs