Skip to content

[RISCV] Match gather(splat(ptr)) as zero strided load #65769

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
preames merged 1 commit into from
Sep 8, 2023
Merged

[RISCV] Match gather(splat(ptr)) as zero strided load #65769

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
30 changes: 20 additions & 10 deletions llvm/lib/Target/RISCV/RISCVGatherScatterLowering.cpp
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -67,7 +67,7 @@ class RISCVGatherScatterLowering : public FunctionPass {
bool tryCreateStridedLoadStore(IntrinsicInst *II, Type *DataType, Value *Ptr,
Value *AlignOp);

std::pair<Value *, Value *> determineBaseAndStride(GetElementPtrInst *GEP,
std::pair<Value *, Value *> determineBaseAndStride(Instruction *Ptr,
IRBuilderBase &Builder);

bool matchStridedRecurrence(Value *Index, Loop *L, Value *&Stride,
Expand Down Expand Up @@ -321,9 +321,19 @@ bool RISCVGatherScatterLowering::matchStridedRecurrence(Value *Index, Loop *L,
}

std::pair<Value *, Value *>
RISCVGatherScatterLowering::determineBaseAndStride(GetElementPtrInst *GEP,
RISCVGatherScatterLowering::determineBaseAndStride(Instruction *Ptr,
IRBuilderBase &Builder) {

// A gather/scatter of a splat is a zero strided load/store.
if (auto *BasePtr = getSplatValue(Ptr)) {
Type *IntPtrTy = DL->getIntPtrType(BasePtr->getType());
return std::make_pair(BasePtr, ConstantInt::get(IntPtrTy, 0));
}

auto *GEP = dyn_cast<GetElementPtrInst>(Ptr);
if (!GEP)
return std::make_pair(nullptr, nullptr);

auto I = StridedAddrs.find(GEP);
if (I != StridedAddrs.end())
return I->second;
Expand Down Expand Up @@ -452,17 +462,17 @@ bool RISCVGatherScatterLowering::tryCreateStridedLoadStore(IntrinsicInst *II,
if (!TLI->isTypeLegal(DataTypeVT))
return false;

// Pointer should be a GEP.
auto *GEP = dyn_cast<GetElementPtrInst>(Ptr);
if (!GEP)
// Pointer should be an instruction.
auto *PtrI = dyn_cast<Instruction>(Ptr);
if (!PtrI)
return false;

LLVMContext &Ctx = GEP->getContext();
LLVMContext &Ctx = PtrI->getContext();
IRBuilder<InstSimplifyFolder> Builder(Ctx, *DL);
Builder.SetInsertPoint(GEP);
Builder.SetInsertPoint(PtrI);

Value *BasePtr, *Stride;
std::tie(BasePtr, Stride) = determineBaseAndStride(GEP, Builder);
std::tie(BasePtr, Stride) = determineBaseAndStride(PtrI, Builder);
if (!BasePtr)
return false;
assert(Stride != nullptr);
Expand All @@ -485,8 +495,8 @@ bool RISCVGatherScatterLowering::tryCreateStridedLoadStore(IntrinsicInst *II,
II->replaceAllUsesWith(Call);
II->eraseFromParent();

if (GEP->use_empty())
RecursivelyDeleteTriviallyDeadInstructions(GEP);
if (PtrI->use_empty())
RecursivelyDeleteTriviallyDeadInstructions(PtrI);

return true;
}
Expand Down
47 changes: 3 additions & 44 deletions llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12918,60 +12918,19 @@ define <4 x i32> @mgather_broadcast_load_unmasked2(ptr %base) {
; RV32-LABEL: mgather_broadcast_load_unmasked2:
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV32-NEXT: vmv.v.x v8, a0
; RV32-NEXT: vluxei32.v v8, (zero), v8
; RV32-NEXT: vlse32.v v8, (a0), zero
; RV32-NEXT: ret
;
; RV64V-LABEL: mgather_broadcast_load_unmasked2:
; RV64V: # %bb.0:
; RV64V-NEXT: vsetivli zero, 4, e64, m2, ta, ma
; RV64V-NEXT: vmv.v.x v10, a0
; RV64V-NEXT: vsetvli zero, zero, e32, m1, ta, ma
; RV64V-NEXT: vluxei64.v v8, (zero), v10
; RV64V-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64V-NEXT: vlse32.v v8, (a0), zero
; RV64V-NEXT: ret
;
; RV64ZVE32F-LABEL: mgather_broadcast_load_unmasked2:
; RV64ZVE32F: # %bb.0:
; RV64ZVE32F-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
; RV64ZVE32F-NEXT: vmset.m v8
; RV64ZVE32F-NEXT: vmv.x.s a1, v8
; RV64ZVE32F-NEXT: # implicit-def: $v8
; RV64ZVE32F-NEXT: beqz zero, .LBB100_5
; RV64ZVE32F-NEXT: # %bb.1: # %else
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: bnez a2, .LBB100_6
; RV64ZVE32F-NEXT: .LBB100_2: # %else2
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: bnez a2, .LBB100_7
; RV64ZVE32F-NEXT: .LBB100_3: # %else5
; RV64ZVE32F-NEXT: andi a1, a1, 8
; RV64ZVE32F-NEXT: bnez a1, .LBB100_8
; RV64ZVE32F-NEXT: .LBB100_4: # %else8
; RV64ZVE32F-NEXT: ret
; RV64ZVE32F-NEXT: .LBB100_5: # %cond.load
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vlse32.v v8, (a0), zero
; RV64ZVE32F-NEXT: andi a2, a1, 2
; RV64ZVE32F-NEXT: beqz a2, .LBB100_2
; RV64ZVE32F-NEXT: .LBB100_6: # %cond.load1
; RV64ZVE32F-NEXT: lw a2, 0(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 2, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 1
; RV64ZVE32F-NEXT: andi a2, a1, 4
; RV64ZVE32F-NEXT: beqz a2, .LBB100_3
; RV64ZVE32F-NEXT: .LBB100_7: # %cond.load4
; RV64ZVE32F-NEXT: lw a2, 0(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 3, e32, m1, tu, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a2
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 2
; RV64ZVE32F-NEXT: andi a1, a1, 8
; RV64ZVE32F-NEXT: beqz a1, .LBB100_4
; RV64ZVE32F-NEXT: .LBB100_8: # %cond.load7
; RV64ZVE32F-NEXT: lw a0, 0(a0)
; RV64ZVE32F-NEXT: vsetivli zero, 4, e32, m1, ta, ma
; RV64ZVE32F-NEXT: vmv.s.x v9, a0
; RV64ZVE32F-NEXT: vslideup.vi v8, v9, 3
; RV64ZVE32F-NEXT: ret
%head = insertelement <4 x i1> poison, i1 true, i32 0
%allones = shufflevector <4 x i1> %head, <4 x i1> poison, <4 x i32> zeroinitializer
Expand Down