[AArch64] Mark Armv8.4-a LDAPUR* instructions as mayLoad #171142

c-rhodes · 2025-12-08T14:54:06Z

Thanks to @cofibrant for spotting.

@cofibrant

Thanks to @cofibrant for spotting.

llvmbot · 2025-12-08T14:54:42Z

@llvm/pr-subscribers-backend-aarch64

Author: Cullen Rhodes (c-rhodes)

Changes

Thanks to @cofibrant for spotting.

Full diff: https://github.com/llvm/llvm-project/pull/171142.diff

7 Files Affected:

(modified) llvm/lib/Target/AArch64/AArch64InstrFormats.td (+1)
(modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s (+5-5)
(modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s (+5-5)
(modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s (+5-5)
(modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s (+5-5)
(modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s (+5-5)
(modified) llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s (+5-5)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrFormats.td b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
index 4d2e740779961..6017f5b1abea0 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrFormats.td
@@ -4384,6 +4384,7 @@ class BaseLoadStoreUnscale<bits<2> sz, bit V, bits<2> opc, dag oops, dag iops,
 // Armv8.4 LDAPR & STLR with Immediate Offset instruction
 multiclass BaseLoadUnscaleV84<string asm, bits<2> sz, bits<2> opc,
                               DAGOperand regtype > {
+  let mayLoad = 1 in
   def i : BaseLoadStoreUnscale<sz, 0, opc, (outs regtype:$Rt),
                                (ins GPR64sp:$Rn, simm9:$offset), asm, []>,
           Sched<[WriteST]> {
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s
index cd3d7e0bf1b57..fac107ddc5326 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s
@@ -14,11 +14,11 @@
 # CHECK-NEXT:  2      1     0.50    *                   ldapur	x20, [x13]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurb	w13, [x17]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurh	w3, [x22]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	w7, [x8]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	x29, [x7]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	w17, [x19]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	x3, [x3]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursw	x3, [x18]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	w7, [x8]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	x29, [x7]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	w17, [x19]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	x3, [x3]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursw	x3, [x18]
 # CHECK-NEXT:  2      1     0.50           *            stlur	w3, [x27]
 # CHECK-NEXT:  2      1     0.50           *            stlur	x23, [x25]
 # CHECK-NEXT:  2      1     0.50           *            stlurb	w30, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s
index 6faa5e1f4db1b..3442dd4eaff67 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/N3-rcpc-immo-instructions.s
@@ -14,11 +14,11 @@
 # CHECK-NEXT:  2      1     0.50    *                   ldapur	x20, [x13]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurb	w13, [x17]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurh	w3, [x22]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	w7, [x8]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	x29, [x7]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	w17, [x19]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	x3, [x3]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursw	x3, [x18]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	w7, [x8]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	x29, [x7]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	w17, [x19]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	x3, [x3]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursw	x3, [x18]
 # CHECK-NEXT:  2      1     0.50           *            stlur	w3, [x27]
 # CHECK-NEXT:  2      1     0.50           *            stlur	x23, [x25]
 # CHECK-NEXT:  2      1     0.50           *            stlurb	w30, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s
index 5c9b43a0e5121..76380b499c907 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V1-rcpc-immo-instructions.s
@@ -14,11 +14,11 @@
 # CHECK-NEXT:  2      1     0.50    *                   ldapur	x20, [x13]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurb	w13, [x17]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurh	w3, [x22]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	w7, [x8]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	x29, [x7]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	w17, [x19]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	x3, [x3]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursw	x3, [x18]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	w7, [x8]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	x29, [x7]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	w17, [x19]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	x3, [x3]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursw	x3, [x18]
 # CHECK-NEXT:  2      1     0.50           *            stlur	w3, [x27]
 # CHECK-NEXT:  2      1     0.50           *            stlur	x23, [x25]
 # CHECK-NEXT:  2      1     0.50           *            stlurb	w30, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s
index 71fd689522215..a099fb965a7a0 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V2-rcpc-immo-instructions.s
@@ -14,11 +14,11 @@
 # CHECK-NEXT:  2      1     0.50    *                   ldapur	x20, [x13]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurb	w13, [x17]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurh	w3, [x22]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	w7, [x8]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	x29, [x7]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	w17, [x19]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	x3, [x3]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursw	x3, [x18]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	w7, [x8]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	x29, [x7]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	w17, [x19]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	x3, [x3]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursw	x3, [x18]
 # CHECK-NEXT:  2      1     0.50           *            stlur	w3, [x27]
 # CHECK-NEXT:  2      1     0.50           *            stlur	x23, [x25]
 # CHECK-NEXT:  2      1     0.50           *            stlurb	w30, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s
index a48978ce8b94d..78542b8b93702 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3-rcpc-immo-instructions.s
@@ -14,11 +14,11 @@
 # CHECK-NEXT:  2      1     0.50    *                   ldapur	x20, [x13]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurb	w13, [x17]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurh	w3, [x22]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	w7, [x8]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	x29, [x7]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	w17, [x19]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	x3, [x3]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursw	x3, [x18]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	w7, [x8]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	x29, [x7]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	w17, [x19]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	x3, [x3]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursw	x3, [x18]
 # CHECK-NEXT:  2      1     0.50           *            stlur	w3, [x27]
 # CHECK-NEXT:  2      1     0.50           *            stlur	x23, [x25]
 # CHECK-NEXT:  2      1     0.50           *            stlurb	w30, [x17]
diff --git a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s
index f801a18bc7a06..1021f80306adb 100644
--- a/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s
+++ b/llvm/test/tools/llvm-mca/AArch64/Neoverse/V3AE-rcpc-immo-instructions.s
@@ -14,11 +14,11 @@
 # CHECK-NEXT:  2      1     0.50    *                   ldapur	x20, [x13]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurb	w13, [x17]
 # CHECK-NEXT:  2      1     0.50    *                   ldapurh	w3, [x22]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	w7, [x8]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursb	x29, [x7]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	w17, [x19]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursh	x3, [x3]
-# CHECK-NEXT:  2      1     0.50                  U     ldapursw	x3, [x18]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	w7, [x8]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	x29, [x7]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	w17, [x19]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	x3, [x3]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursw	x3, [x18]
 # CHECK-NEXT:  2      1     0.50           *            stlur	w3, [x27]
 # CHECK-NEXT:  2      1     0.50           *            stlur	x23, [x25]
 # CHECK-NEXT:  2      1     0.50           *            stlurb	w30, [x17]

cofibrant · 2025-12-08T14:58:06Z

llvm/test/tools/llvm-mca/AArch64/Neoverse/N2-rcpc-immo-instructions.s

+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	w7, [x8]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursb	x29, [x7]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	w17, [x19]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursh	x3, [x3]
+# CHECK-NEXT:  2      1     0.50    *             U     ldapursw	x3, [x18]


I'm surprised these are still marked as 'has side effects'. Could you explain what the side effects are?

yeah tbh im not sure about that either, i can't see why they shouldn't be marked as mayLoad so I suspect that was just an oversight, but I didnt add these instructions

The context is that I spotted that Apple clang thinks these instructions may load and do not have side effects and I wanted to understand which implementation is correct (if either) and fix accordingly

I'm not familiar with the semantics of these instructions, but from a quick glance at https://developer.arm.com/documentation/102336/0100/Load-Acquire-and-Store-Release-instructions it looks like they have implicit barrier semantics, so while I can't give a definitive answer I would err more towards them having side-effects than not. dmb instructions do, and these have less constrained but similar semantics it seems.

Interesting, thanks!

davemgreen

I presume the other instructions get this from the patterns? They should have atomic side-effects but from the other instructions that I believe that usually comes from the MMO. HasSideEffects should be stronger so wouldn't make it incorrect to keep.

davemgreen · 2025-12-08T14:59:35Z

llvm/lib/Target/AArch64/AArch64InstrFormats.td

+  let mayLoad = 1 in
  def i : BaseLoadStoreUnscale<sz, 0, opc, (outs regtype:$Rt),
                               (ins GPR64sp:$Rn, simm9:$offset), asm, []>,
          Sched<[WriteST]> {


This should probably be WriteLD or WriteAtomic. The scheduling info in the tests looks incorrect.

Good spot! I can post a separate PR.

FWIW I've not been paying close attention to the scheduling info with recent patches tbh, just trying to refactor the tests and increase coverage but i can believe there's many with bad info such as this.

posted a fix for this #171637

c-rhodes · 2025-12-08T16:40:25Z

I presume the other instructions get this from the patterns?

ah ok, I didnt realise this until I saw your comment but seems so, when I remove

llvm-project/llvm/lib/Target/AArch64/AArch64InstrAtomics.td

Lines 602 to 633 in 614fe6d

    
           // v8.4a FEAT_LRCPC2 patterns 
        
           let Predicates = [HasRCPC_IMMO, UseLDAPUR] in { 
        
             // Load-Acquire RCpc Register unscaled loads 
        
             def : Pat<(acquiring_load<atomic_load_azext_8> 
        
                          (am_unscaled8 GPR64sp:$Rn, simm9:$offset)), 
        
                     (LDAPURBi GPR64sp:$Rn, simm9:$offset)>; 
        
             def : Pat<(acquiring_load<atomic_load_azext_16> 
        
                          (am_unscaled16 GPR64sp:$Rn, simm9:$offset)), 
        
                     (LDAPURHi GPR64sp:$Rn, simm9:$offset)>; 
        
             def : Pat<(acquiring_load<atomic_load_nonext_32> 
        
                          (am_unscaled32 GPR64sp:$Rn, simm9:$offset)), 
        
                     (LDAPURi GPR64sp:$Rn, simm9:$offset)>; 
        
             def : Pat<(acquiring_load<atomic_load_nonext_64> 
        
                          (am_unscaled64 GPR64sp:$Rn, simm9:$offset)), 
        
                     (LDAPURXi GPR64sp:$Rn, simm9:$offset)>; 
        
           } 
        
           let Predicates = [HasRCPC_IMMO] in { 
        
             // Store-Release Register unscaled stores 
        
             def : Pat<(releasing_store<atomic_store_8> 
        
                          (am_unscaled8 GPR64sp:$Rn, simm9:$offset), GPR32:$val), 
        
                     (STLURBi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>; 
        
             def : Pat<(releasing_store<atomic_store_16> 
        
                          (am_unscaled16 GPR64sp:$Rn, simm9:$offset), GPR32:$val), 
        
                     (STLURHi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>; 
        
             def : Pat<(releasing_store<atomic_store_32> 
        
                          (am_unscaled32 GPR64sp:$Rn, simm9:$offset), GPR32:$val), 
        
                     (STLURWi GPR32:$val, GPR64sp:$Rn, simm9:$offset)>; 
        
             def : Pat<(releasing_store<atomic_store_64> 
        
                          (am_unscaled64 GPR64sp:$Rn, simm9:$offset), GPR64:$val), 
        
                     (STLURXi GPR64:$val, GPR64sp:$Rn, simm9:$offset)>; 
        
           }

all of these instructions then just have HasSideEffects.

They should have atomic side-effects but from the other instructions that I believe that usually comes from the MMO. HasSideEffects should be stronger so wouldn't make it incorrect to keep.

ok thanks for the context, I think I can see that now

llvm-project/llvm/lib/Target/AArch64/AArch64InstrAtomics.td

Line 40 in 614fe6d

let IsAtomic = 1;

This isn't set on the instruction so I guess HasSideEffects is best we can do for ldapurs[bhw]?

cofibrant · 2025-12-09T17:29:08Z

I should be able to post a patch including some ISel patterns for these instructions in the next couple of days. From these the compiler is able to infer MayLoad without this patch.

c-rhodes · 2025-12-10T08:57:16Z

I should be able to post a patch including some ISel patterns for these instructions in the next couple of days. From these the compiler is able to infer MayLoad without this patch.

ah nice, I'll hold off on landing this for now then

[AArch64] Mark Armv8.4-a LDAPUR* instructions as mayLoad

597623c

Thanks to @cofibrant for spotting.

c-rhodes requested review from cofibrant, davemgreen and sjoerdmeijer December 8, 2025 14:54

llvmbot added the backend:AArch64 label Dec 8, 2025

c-rhodes mentioned this pull request Dec 8, 2025

[llvm-mca][AArch64] Refactor Neoverse tests to split out common inputs (NFC) #170324

Merged

cofibrant reviewed Dec 8, 2025

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davemgreen approved these changes Dec 8, 2025

View reviewed changes

cofibrant mentioned this pull request Dec 11, 2025

[AArch64] Add ISel patterns for LDAPURS* instructions #171788

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[AArch64] Mark Armv8.4-a LDAPUR* instructions as mayLoad #171142

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[AArch64] Mark Armv8.4-a LDAPUR* instructions as mayLoad #171142

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