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expandFMINIMUMNUM_FMAXIMUMNUM: Improve compare between zeros #140193

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Merged
wzssyqa merged 8 commits into from
Dec 4, 2025
Merged

expandFMINIMUMNUM_FMAXIMUMNUM: Improve compare between zeros #140193

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5735e20
expandFMINIMUMNUM_FMAXIMUMNUM: Improve compare between zeros
wzssyqa Dec 3, 2025
54f99ad
Update llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
wzssyqa Dec 3, 2025
7049d73
Add testcase for aarch64 and x86
wzssyqa Dec 3, 2025
fc89739
Fix code style
wzssyqa Dec 3, 2025
d06323b
Update testcase
wzssyqa Dec 3, 2025
dbd52dd
Update x86 tests
wzssyqa Dec 4, 2025
5f4cfe0
lways prefer RHS if equal
wzssyqa Dec 4, 2025
59bd3e6
isOperationLegalOrCustom(ISD::IS_FPCLASS, VT)
wzssyqa Dec 4, 2025
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19 changes: 13 additions & 6 deletions llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -8852,6 +8852,7 @@ SDValue TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *Node,
RHS = DAG.getSelectCC(DL, RHS, RHS, LHS, RHS, ISD::SETUO);
}

// Always prefer RHS if equal.
SDValue MinMax =
DAG.getSelectCC(DL, LHS, RHS, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT);

Expand All @@ -8866,13 +8867,19 @@ SDValue TargetLowering::expandFMINIMUMNUM_FMAXIMUMNUM(SDNode *Node,
DAG.getTargetConstant(IsMax ? fcPosZero : fcNegZero, DL, MVT::i32);
SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax,
DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ);
SDValue LCmp = DAG.getSelect(
DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHS, TestZero), LHS,
EVT IntVT = VT.changeTypeToInteger();
EVT FloatVT = VT.changeElementType(MVT::f32);
SDValue LHSTrunc = LHS;
if (!isTypeLegal(IntVT) && !isOperationLegalOrCustom(ISD::IS_FPCLASS, VT)) {
LHSTrunc = DAG.getNode(ISD::FP_ROUND, DL, FloatVT, LHS,
DAG.getIntPtrConstant(0, DL, /*isTarget=*/true));
}
// It's OK to select from LHS and MinMax, with only one ISD::IS_FPCLASS, as
// we preferred RHS when generate MinMax, if the operands are equal.
SDValue RetZero = DAG.getSelect(
DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHSTrunc, TestZero), LHS,
MinMax, Flags);
SDValue RCmp = DAG.getSelect(
DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, RHS, TestZero), RHS, LCmp,
Flags);
return DAG.getSelect(DL, VT, IsZero, RCmp, MinMax, Flags);
return DAG.getSelect(DL, VT, IsZero, RetZero, MinMax, Flags);
}

/// Returns a true value if if this FPClassTest can be performed with an ordered
Expand Down
124 changes: 124 additions & 0 deletions llvm/test/CodeGen/AArch64/fp-maximumnum-minimumnum.ll
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Original file line number Diff line number Diff line change
Expand Up @@ -1076,6 +1076,68 @@ entry:
ret <16 x half> %c
}

;;;;;;;;;;;;;;;; max_f128
define fp128 @max_fp128(fp128 %x, fp128 %y) {
; AARCH64-LABEL: max_fp128:
; AARCH64: // %bb.0: // %start
; AARCH64-NEXT: sub sp, sp, #48
; AARCH64-NEXT: str x30, [sp, #32] // 8-byte Spill
; AARCH64-NEXT: .cfi_def_cfa_offset 48
; AARCH64-NEXT: .cfi_offset w30, -16
; AARCH64-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: bl __unordtf2
; AARCH64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.eq .LBB32_2
; AARCH64-NEXT: // %bb.1: // %start
; AARCH64-NEXT: str q0, [sp] // 16-byte Spill
; AARCH64-NEXT: .LBB32_2: // %start
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: bl __unordtf2
; AARCH64-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.eq .LBB32_4
; AARCH64-NEXT: // %bb.3: // %start
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: .LBB32_4: // %start
; AARCH64-NEXT: ldr q0, [sp] // 16-byte Reload
; AARCH64-NEXT: str q1, [sp, #16] // 16-byte Spill
; AARCH64-NEXT: bl __gttf2
; AARCH64-NEXT: ldr q0, [sp] // 16-byte Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.le .LBB32_6
; AARCH64-NEXT: // %bb.5: // %start
; AARCH64-NEXT: str q0, [sp, #16] // 16-byte Spill
; AARCH64-NEXT: .LBB32_6: // %start
; AARCH64-NEXT: str q0, [sp] // 16-byte Spill
; AARCH64-NEXT: bl __trunctfsf2
; AARCH64-NEXT: fmov w8, s0
; AARCH64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: cmp w8, #0
; AARCH64-NEXT: b.ne .LBB32_8
; AARCH64-NEXT: // %bb.7: // %start
; AARCH64-NEXT: ldr q1, [sp] // 16-byte Reload
; AARCH64-NEXT: .LBB32_8: // %start
; AARCH64-NEXT: adrp x8, .LCPI32_0
; AARCH64-NEXT: str q1, [sp] // 16-byte Spill
; AARCH64-NEXT: ldr q1, [x8, :lo12:.LCPI32_0]
; AARCH64-NEXT: bl __eqtf2
; AARCH64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.ne .LBB32_10
; AARCH64-NEXT: // %bb.9: // %start
; AARCH64-NEXT: ldr q0, [sp] // 16-byte Reload
; AARCH64-NEXT: .LBB32_10: // %start
; AARCH64-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; AARCH64-NEXT: add sp, sp, #48
; AARCH64-NEXT: ret
start:
%0 = tail call fp128 @llvm.maximumnum.f128(fp128 %x, fp128 %y)
ret fp128 %0
}

;;;;;;;;;;;;;;;; max_f64
define double @max_f64(double %a, double %b) {
; AARCH64-LABEL: max_f64:
Expand Down Expand Up @@ -1658,6 +1720,68 @@ entry:
ret <16 x half> %c
}

;;;;;;;;;;;;;;;; min_f128
define fp128 @min_fp128(fp128 %x, fp128 %y) {
; AARCH64-LABEL: min_fp128:
; AARCH64: // %bb.0: // %start
; AARCH64-NEXT: sub sp, sp, #48
; AARCH64-NEXT: str x30, [sp, #32] // 8-byte Spill
; AARCH64-NEXT: .cfi_def_cfa_offset 48
; AARCH64-NEXT: .cfi_offset w30, -16
; AARCH64-NEXT: stp q0, q1, [sp] // 32-byte Folded Spill
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: bl __unordtf2
; AARCH64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.eq .LBB49_2
; AARCH64-NEXT: // %bb.1: // %start
; AARCH64-NEXT: str q0, [sp] // 16-byte Spill
; AARCH64-NEXT: .LBB49_2: // %start
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: bl __unordtf2
; AARCH64-NEXT: ldp q0, q1, [sp] // 32-byte Folded Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.eq .LBB49_4
; AARCH64-NEXT: // %bb.3: // %start
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: .LBB49_4: // %start
; AARCH64-NEXT: ldr q0, [sp] // 16-byte Reload
; AARCH64-NEXT: str q1, [sp, #16] // 16-byte Spill
; AARCH64-NEXT: bl __gttf2
; AARCH64-NEXT: ldr q0, [sp] // 16-byte Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.le .LBB49_6
; AARCH64-NEXT: // %bb.5: // %start
; AARCH64-NEXT: str q0, [sp, #16] // 16-byte Spill
; AARCH64-NEXT: .LBB49_6: // %start
; AARCH64-NEXT: str q0, [sp] // 16-byte Spill
; AARCH64-NEXT: bl __trunctfsf2
; AARCH64-NEXT: fmov w8, s0
; AARCH64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; AARCH64-NEXT: mov v1.16b, v0.16b
; AARCH64-NEXT: cmp w8, #0
; AARCH64-NEXT: b.ne .LBB49_8
; AARCH64-NEXT: // %bb.7: // %start
; AARCH64-NEXT: ldr q1, [sp] // 16-byte Reload
; AARCH64-NEXT: .LBB49_8: // %start
; AARCH64-NEXT: adrp x8, .LCPI49_0
; AARCH64-NEXT: str q1, [sp] // 16-byte Spill
; AARCH64-NEXT: ldr q1, [x8, :lo12:.LCPI49_0]
; AARCH64-NEXT: bl __eqtf2
; AARCH64-NEXT: ldr q0, [sp, #16] // 16-byte Reload
; AARCH64-NEXT: cmp w0, #0
; AARCH64-NEXT: b.ne .LBB49_10
; AARCH64-NEXT: // %bb.9: // %start
; AARCH64-NEXT: ldr q0, [sp] // 16-byte Reload
; AARCH64-NEXT: .LBB49_10: // %start
; AARCH64-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; AARCH64-NEXT: add sp, sp, #48
; AARCH64-NEXT: ret
start:
%0 = tail call fp128 @llvm.maximumnum.f128(fp128 %x, fp128 %y)
ret fp128 %0
}

;;;;;;;;;;;;;;;; min_f64
define double @min_f64(double %a, double %b) {
; AARCH64-LABEL: min_f64:
Expand Down
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