[CIR][CodeGen] Add support for x86 memory fence

[shrikardongre]

No description provided.

[github-actions]

✅ With the latest revision this PR passed the C/C++ code formatter.

[shrikardongre]

@bcardosolopes @FantasqueX can you please review this PR as I am getting the test fails due to the filecheck issue , Can you help me understand how exactly i have to modify the rdtsc test case . The CIR that I am able to generate is :

  cir.func no_proto @test_rdtsc() -> !s32i extra(#fn_attr) {
    %0 = cir.alloca !s32i, !cir.ptr<!s32i>, ["__retval"] {alignment = 4 : i64} loc(#loc23)
    %1 = cir.get_global @_rdtsc : !cir.ptr<!cir.func<(...) -> !s32i>> loc(#loc35)
    %2 = cir.cast(bitcast, %1 : !cir.ptr<!cir.func<(...) -> !s32i>>), !cir.ptr<!cir.func<() -> !s32i>> loc(#loc35)
    %3 = cir.call %2() : (!cir.ptr<!cir.func<() -> !s32i>>) -> !s32i loc(#loc24)
    cir.store %3, %0 : !s32i, !cir.ptr<!s32i> loc(#loc36)
    %4 = cir.load %0 : !cir.ptr<!s32i>, !s32i loc(#loc36)
    cir.return %4 : !s32i loc(#loc36)
  } loc(#loc34)

Thank you.

[bcardosolopes]

how exactly i have to modify the rdtsc test case

if that's causing confusion, perhaps remove it from this PR and land first the other intrinsics?

[shrikardongre]

#1523 for BI__rdtsc

[bcardosolopes]

Please rename the PR to be consistent with the new content

[bcardosolopes]

LGTM after changing the title!

[shrikardongre]

done 👍🏻