Feature Description
Automated layout review to detect common layout issues that aren't caught with traditional DRC such as:
- High speed signals crossing reference planes
- Overly large current loop layout for switching power supplies
- Insufficient copper size for expected current draw
Use Case
Doing good design reviews is hard, especially for those new to PCB design.
There is a long list of mistakes or decisions that can cause issues and it is easy to make such mistakes incidentally, e.g. such as using push and shove routing can move existing traces which may go unnoticed.
These issues can be hard to catch with simple design rule checks and a small change can cause drastically worse EMI performance.
- High speed traces should not cross over plane splits or to new reference planes without having the planes decoupled to prevent signal integrity issues and reduce EMI.
- Power supply current loops should be kept to the smallest size possible to reduce EMI
- Ensuring all your routings can handle expected current draw.
Proposed Implementation (optional)
High speed trace checks
- Determine which nets are "high speed", high dV/dT
- Detect where a trace crosses between reference planes
- Check for plane splits/voids on same layer
Power supply current loops
Ensure routings can handle required current
- Calculated expected current draw on net
- Determine copper thickness/trace width to calculate voltage drop/power loss/temperature rise
- Could get the AI to set trace width directives on each net to than have the normal DRC run and determine undersize traces
Additional Context
There is a lot of information related to good layout available in public application notes from various manufacturers.
Feature Description
Automated layout review to detect common layout issues that aren't caught with traditional DRC such as:
Use Case
Doing good design reviews is hard, especially for those new to PCB design.
There is a long list of mistakes or decisions that can cause issues and it is easy to make such mistakes incidentally, e.g. such as using push and shove routing can move existing traces which may go unnoticed.
These issues can be hard to catch with simple design rule checks and a small change can cause drastically worse EMI performance.
Proposed Implementation (optional)
High speed trace checks
Power supply current loops
Ensure routings can handle required current
Additional Context
There is a lot of information related to good layout available in public application notes from various manufacturers.