In Makefile we could substitute a command with an variable, and running with alternatives: `make CC=clang++ test`: ```Makefile CC = g++ test: $(CC) foo.cc ``` Though this is related to Makefile syntax, it might still be worth to consider it. XD
In Makefile we could substitute a command with an variable, and running with alternatives:
make CC=clang++ test:Though this is related to Makefile syntax, it might still be worth to consider it. XD