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[SYCL][CUDA][libclc] Add remaining atomics #5192

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Merged
bader merged 5 commits into from
Jan 18, 2022
Merged

[SYCL][CUDA][libclc] Add remaining atomics #5192

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7cd8c49
[SYCL][CUDA][libclc] implemented atomic min, max and sub
t4c1 Dec 9, 2021
585bfe0
Merge branch 'sycl' into remaining_ptx_atomics
t4c1 Dec 21, 2021
340196d
format
t4c1 Dec 21, 2021
b555211
Merge branch 'sycl' into remaining_ptx_atomics
t4c1 Jan 17, 2022
109a845
format new files
t4c1 Jan 17, 2022
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1 change: 1 addition & 0 deletions libclc/ptx-nvidiacl/libspirv/SOURCES
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Expand Up @@ -95,6 +95,7 @@ atomic/atomic_dec.cl
atomic/atomic_inc.cl
atomic/atomic_max.cl
atomic/atomic_min.cl
atomic/atomic_sub.cl
atomic/atomic_xchg.cl
atomic/atomic_or.cl
atomic/atomic_xor.cl
2 changes: 1 addition & 1 deletion libclc/ptx-nvidiacl/libspirv/atomic/atomic_inc_dec_helpers.h
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Expand Up @@ -23,7 +23,7 @@
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics) { \
return _Z21__spirv_AtomicIAddEXTPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
pointer, scope, semantics, 1); \
pointer, scope, semantics, VAL); \
}

#define __CLC_NVVM_ATOMIC_INCDEC(TYPE, TYPE_MANGLED, OP_MANGLED, VAL) \
Expand Down
51 changes: 51 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_max.cl
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Expand Up @@ -20,3 +20,54 @@ __CLC_NVVM_ATOMIC(unsigned long, m, unsigned long, ul, max,
#undef __CLC_NVVM_ATOMIC_TYPES
#undef __CLC_NVVM_ATOMIC
#undef __CLC_NVVM_ATOMIC_IMPL

#define __CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, \
ADDR_SPACE, ADDR_SPACE_MANGLED) \
TYPE_INT _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
volatile ADDR_SPACE const TYPE_INT *, enum Scope, \
enum MemorySemanticsMask); \
TYPE_INT \
_Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
volatile ADDR_SPACE TYPE_INT *, enum Scope, enum MemorySemanticsMask, enum MemorySemanticsMask, \
TYPE_INT, TYPE_INT); \
_CLC_DECL TYPE \
_Z21__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE val) { \
enum MemorySemanticsMask load_order; \
switch (semantics) { \
case SequentiallyConsistent: \
load_order = SequentiallyConsistent; \
break; \
case Acquire: \
case AcquireRelease: \
load_order = Acquire; \
break; \
default: \
load_order = None; \
} \
volatile ADDR_SPACE TYPE_INT* pointer_int = (volatile ADDR_SPACE TYPE_INT *)pointer; \
TYPE_INT val_int = *(TYPE_INT*)&val; \
TYPE_INT old_int = _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
pointer_int, scope, load_order); \
TYPE old = *(TYPE*)&old_int; \
while (val > old) { \
TYPE_INT tmp_int = _Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
pointer_int, scope, semantics, semantics, val_int, old_int); \
if(old_int == tmp_int){ \
return *(TYPE*)&tmp_int; \
} \
old_int = tmp_int; \
old = *(TYPE*)&old_int; \
} \
return old; \
}

#define __CLC_NVVM_ATOMIC_MAX(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED) \
__CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __global, \
AS1) \
__CLC_NVVM_ATOMIC_MAX_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __local, \
AS3)

__CLC_NVVM_ATOMIC_MAX(float, f, int, i, FMaxEXT)
__CLC_NVVM_ATOMIC_MAX(double, d, long, l, FMaxEXT)
51 changes: 51 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_min.cl
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Expand Up @@ -18,3 +18,54 @@ __CLC_NVVM_ATOMIC(ulong, m, ulong, ul, min, _Z18__spirv_AtomicUMin)
#undef __CLC_NVVM_ATOMIC_TYPES
#undef __CLC_NVVM_ATOMIC
#undef __CLC_NVVM_ATOMIC_IMPL

#define __CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, \
ADDR_SPACE, ADDR_SPACE_MANGLED) \
TYPE_INT _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
volatile ADDR_SPACE const TYPE_INT *, enum Scope, \
enum MemorySemanticsMask); \
TYPE_INT \
_Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
volatile ADDR_SPACE TYPE_INT *, enum Scope, enum MemorySemanticsMask, enum MemorySemanticsMask, \
TYPE_INT, TYPE_INT); \
_CLC_DECL TYPE \
_Z21__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE val) { \
enum MemorySemanticsMask load_order; \
switch (semantics) { \
case SequentiallyConsistent: \
load_order = SequentiallyConsistent; \
break; \
case Acquire: \
case AcquireRelease: \
load_order = Acquire; \
break; \
default: \
load_order = None; \
} \
volatile ADDR_SPACE TYPE_INT* pointer_int = (volatile ADDR_SPACE TYPE_INT *)pointer; \
TYPE_INT val_int = *(TYPE_INT*)&val; \
TYPE_INT old_int = _Z18__spirv_AtomicLoadPU3##ADDR_SPACE_MANGLED##K##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE( \
pointer_int, scope, load_order); \
TYPE old = *(TYPE*)&old_int; \
while (val < old) { \
TYPE_INT tmp_int = _Z29__spirv_AtomicCompareExchange##PU3##ADDR_SPACE_MANGLED##TYPE_INT_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagES5_##TYPE_INT_MANGLED##TYPE_INT_MANGLED( \
pointer_int, scope, semantics, semantics, val_int, old_int); \
if(old_int == tmp_int){ \
return *(TYPE*)&tmp_int; \
} \
old_int = tmp_int; \
old = *(TYPE*)&old_int; \
} \
return old; \
}

#define __CLC_NVVM_ATOMIC_MIN(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED) \
__CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __global, \
AS1) \
__CLC_NVVM_ATOMIC_MIN_IMPL(TYPE, TYPE_MANGLED, TYPE_INT, TYPE_INT_MANGLED, OP_MANGLED, __local, \
AS3)

__CLC_NVVM_ATOMIC_MIN(float, f, int, i, FMinEXT)
__CLC_NVVM_ATOMIC_MIN(double, d, long, l, FMinEXT)
39 changes: 39 additions & 0 deletions libclc/ptx-nvidiacl/libspirv/atomic/atomic_sub.cl
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@@ -0,0 +1,39 @@
//===----------------------------------------------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//


#include <spirv/spirv.h>
#include <spirv/spirv_types.h>

#define __CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, \
ADDR_SPACE, ADDR_SPACE_MANGLED) \
TYPE \
_Z18__spirv_AtomicIAddPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *, enum Scope, enum MemorySemanticsMask, \
TYPE); \
_CLC_DECL TYPE \
_Z18__spirv_Atomic##OP_MANGLED##PU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
volatile ADDR_SPACE TYPE *pointer, enum Scope scope, \
enum MemorySemanticsMask semantics, TYPE val) { \
return _Z18__spirv_AtomicIAddPU3##ADDR_SPACE_MANGLED##TYPE_MANGLED##N5__spv5Scope4FlagENS1_19MemorySemanticsMask4FlagE##TYPE_MANGLED( \
pointer, scope, semantics, -val); \
}

#define __CLC_NVVM_ATOMIC_SUB(TYPE, TYPE_MANGLED, OP_MANGLED) \
__CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, __global, \
AS1) \
__CLC_NVVM_ATOMIC_SUB_IMPL(TYPE, TYPE_MANGLED, OP_MANGLED, __local, \
AS3)

__CLC_NVVM_ATOMIC_SUB(int, i, ISub)
__CLC_NVVM_ATOMIC_SUB(unsigned int, j, ISub)
__CLC_NVVM_ATOMIC_SUB(long, l, ISub)
__CLC_NVVM_ATOMIC_SUB(unsigned long, m, ISub)

#undef __CLC_NVVM_ATOMIC_SUB_IMPL
#undef __CLC_NVVM_ATOMIC_SUB