Sync with SPIR-V Translator de0957d85bcaa #351
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The sync brings the following commits: [de0957d85bcaa] Disabling mem2reg by default [e963d8deacece] Translate __fpga_reg builtin to FPGARegINTEL instruction Signed-off-by: Artem Gindinson <[email protected]>
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Feb 23, 2023
This patch adds 2nd include path <build_dir>/include (in addition to <build_dir>/include/sycl) to LIT infra to add a ability to compile DPC++ code with oneapi and intel extensions which moved from (e.g., for intel) <build_dir>/include/CL/sycl/INTEL to <build_dir>/include/sycl/ext/intel in intel/llvm:intel#4014
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The sync brings the following commits:
[de0957d85bcaa] Disabling mem2reg by default
[e963d8deacece] Translate __fpga_reg builtin to FPGARegINTEL instruction
Signed-off-by: Artem Gindinson [email protected]