Adding buffer_location SPIR-V spec as an extension #2084
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This is used for heterogenous global memory in FPGA targets
MrSidims
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Jul 10, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a articular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel/llvm#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
MrSidims
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Jul 10, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a articular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel/llvm#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
MrSidims
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Jul 13, 2020
MrSidims
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Jul 24, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a articular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel/llvm#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
MrSidims
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Jul 24, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a particular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel/llvm#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
MrSidims
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Jul 24, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a particular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel/llvm#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
MrSidims
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Jul 24, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a particular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel/llvm#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
AlexeySotkin
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Jul 27, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a particular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel/llvm#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
alexbatashev
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Jul 28, 2020
This extension adds a function parameter decoration that is useful for FPGA targets. This decoration indicates that a particular global memory pointer can only access a particular physical memory location. Knowing this information at compile time can allow FPGA compilers to generate load store units of lower area for accesses done through such a pointer. Specification: intel#2084 Signed-off-by: Dmitry Sidorov <[email protected]>
Contributor
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@intel/dpcpp-specification-reviewers, could you take a look, please? |
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Contributor
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@intel/dpcpp-specification-reviewers, could you take a look, please? |
bader
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Contributor
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@ajaykumarkannan @tiwaria1 @GarveyJoe could some of you re-create this PR? Also can we consider this extension to be finished or other changes are required? |
Contributor
I will try to re-start upstreaming the buffer_location property. If I cannot get to it by then I will find a different owner. |
jsji
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Jul 17, 2023
This fixes most of the tests to use -emit-opaque-pointers. There are a few tests not yet converted for various reasons: Several tests only have check lines for opaque struct declarations. These are not emitted in opaque pointer mode, so the tests need deeper rewrites. A few tests check both typed and opaque pointer output. A few tests only make sense with typed pointer output (ForwardPtr.ll and RecursiveType.ll in particular). One test has a crash in reverse translation. Outside of these cases, all tests should now be using opaque pointer for testing reverse translation. Original commit: KhronosGroup/SPIRV-LLVM-Translator@0dc80be
Chenyang-L
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Jul 31, 2023
This reverts commit 6a57011.
jsji
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Aug 11, 2023
This fixes most of the tests to use -emit-opaque-pointers. There are a few tests not yet converted for various reasons: Several tests only have check lines for opaque struct declarations. These are not emitted in opaque pointer mode, so the tests need deeper rewrites. A few tests check both typed and opaque pointer output. A few tests only make sense with typed pointer output (ForwardPtr.ll and RecursiveType.ll in particular). One test has a crash in reverse translation. Outside of these cases, all tests should now be using opaque pointer for testing reverse translation. Original commit: KhronosGroup/SPIRV-LLVM-Translator@0dc80be
kbenzie
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Feb 17, 2025
Pass -q to `clang-offload-extract` so it doesn't generate binary names when building. Closes: intel#2084
Chenyang-L
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Feb 18, 2025
Pass -q to `clang-offload-extract` so it doesn't generate binary names when building. Closes: #2084
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This is used for heterogenous global memory in FPGA targets