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[SYCL] Support for load/store cache controls #11584
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| Original file line number | Diff line number | Diff line change | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|
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@@ -42,6 +42,9 @@ constexpr uint32_t SPIRV_HOST_ACCESS_DEFAULT_VALUE = 2; // Read/Write | |||||||||
| constexpr uint32_t SPIRV_INITIATION_INTERVAL_DECOR = 5917; | ||||||||||
| constexpr uint32_t SPIRV_PIPELINE_ENABLE_DECOR = 5919; | ||||||||||
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| constexpr uint32_t SPIRV_CACHE_CONTROL_READ_DECOR = 6442; | ||||||||||
| constexpr uint32_t SPIRV_CACHE_CONTROL_WRITE_DECOR = 6443; | ||||||||||
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| enum class DecorValueTy { | ||||||||||
| uint32, | ||||||||||
| boolean, | ||||||||||
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@@ -97,6 +100,95 @@ MDNode *buildSpirvDecorMetadata(LLVMContext &Ctx, uint32_t OpCode, | |||||||||
| return MDNode::get(Ctx, MD); | ||||||||||
| } | ||||||||||
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| /// Builds a metadata node for a SPIR-V decoration for cache controls | ||||||||||
| /// where decoration code and value are both uint32_t integers. | ||||||||||
| /// The value encodes a cache level and a cache control type. | ||||||||||
| /// | ||||||||||
| /// @param Ctx [in] the LLVM Context. | ||||||||||
| /// @param Name [in] the SPIR-V property string name. | ||||||||||
| /// @param OpCode [in] the SPIR-V opcode. | ||||||||||
| /// @param CacheMode [in] whether read or write. | ||||||||||
| /// @param CacheLevel [in] the cache level. | ||||||||||
| /// | ||||||||||
| /// @returns a pointer to the metadata node created for the required decoration | ||||||||||
| /// and its values. | ||||||||||
| MDNode *buildSpirvDecorCacheProp(LLVMContext &Ctx, StringRef Name, | ||||||||||
| uint32_t OpCode, uint32_t CacheMode, | ||||||||||
| uint32_t CacheLevel) { | ||||||||||
| // SPIR-V encodings of read control | ||||||||||
| enum cache_control_read_type { | ||||||||||
| read_uncached = 0, | ||||||||||
| read_cached = 1, | ||||||||||
| read_streaming = 2, | ||||||||||
| read_invalidate = 3, | ||||||||||
| read_const_cached = 4 | ||||||||||
| }; | ||||||||||
| // SPIR-V encodings of write control | ||||||||||
| enum cache_control_write_type { | ||||||||||
| write_uncached = 0, | ||||||||||
| write_through = 1, | ||||||||||
| write_back = 2, | ||||||||||
| write_streaming = 3 | ||||||||||
| }; | ||||||||||
| // SYCL encodings of read/write control | ||||||||||
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| enum cache_mode { | ||||||||||
| uncached, | ||||||||||
| cached, | ||||||||||
| streaming, | ||||||||||
| invalidate, | ||||||||||
| const_cached, | ||||||||||
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| const_cached, | |
| constant |
cache_mode::const_cached has some redundancy compared to cache_mode::constant.
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OK
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I'd prefer:
| through, | |
| back | |
| write_through, | |
| write_back |
I think including "write" in the name here would help readability. These are established terms for how caches work, whereas "through" and "back" by themselves are not. Including "write" in the name here also makes it clear that passing these two modes through to read_hint will give an error.
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These are not user-visible, but I'll make the change you suggest.
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Is there a design document or specifications for LLVM/SPIR-V levels?
Cache controls are using annotated pointer design. Right?
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The SPIR-V extension is here: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/INTEL/SPV_INTEL_cache_controls.asciidoc
This implementation builds upon annotated_ptr by adding new properties.
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Thanks. I also find KhronosGroup/SPIRV-LLVM-Translator#2140, which documents the LLVM IR representation of cache controls.