igzip/riscv64: Optimize adler32_rvv for VLEN=128#390
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leiwen2025 wants to merge 1 commit intointel:masterfrom
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igzip/riscv64: Optimize adler32_rvv for VLEN=128#390leiwen2025 wants to merge 1 commit intointel:masterfrom
leiwen2025 wants to merge 1 commit intointel:masterfrom
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Contributor
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@leiwen2025 could you update Release notes saying Adler32 has been optimized for RISCV? |
Contributor
Author
Done. I've updated the Release notes. |
Contributor
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@sunyuechi could you review this PR? Thanks! |
sunyuechi
reviewed
Feb 8, 2026
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| vsetvli zero, t0, e32, m8, ta, ma | ||
| vmv.v.i v8, 0 | ||
| vmv.v.i v24, 0 |
sunyuechi
reviewed
Feb 8, 2026
| vsetvli zero, t0, e16, m4, ta, ma | ||
| vsetvli zero, t0, e16, m2, ta, ma | ||
| vwaddu.wv v24, v24, v16 | ||
| vwaddu.wv v24, v24, v18 |
Contributor
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The above 2 lines are just vwaddu.vv v24, v16, v18? And vwaddu.vv doesn't require register zero-clearing either.
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vwaddu.vv v24, v16 ,v18 cannot implement the correct logic. The logic should be v24 += v16 + v18
sunyuechi
reviewed
Feb 9, 2026
| li t0, 32 | ||
| bltu a2, t0, tail_bytes | ||
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| vsetvli zero, t0, e32, m8, ta, ma |
Contributor
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LGTM (please squash commits). |
Signed-off-by: WenLei <lei.wen2@zte.com.cn>
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Contributor
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This is merged now, thanks. |
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This PR optimizes the adler32_rvv implementation for vlen=128.
The optimization has been verified on the SG2044 platform: