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RISCV64 JIT BUG #20351

Description

@xfan1024

RISCV64 JIT translates IROp::FRSqrt to native code like this:

fsqrt.s ft6,ft5
lui     a0,0x3f800
fmv.d.x ft7,a0
fdiv.s  ft6,ft7,ft6

After the fdiv.s instruction, the value in ft6 becomes NaN.

According to riscv-spec-v2.2

When multiple oating-point precisions are supported, then valid values of narrower n-bit types,
n < FLEN, are represented in the lower n bits of an FLEN-bit NaN value, in a process termed
NaN-boxing. The upper bits of a valid NaN-boxed value must be all 1s. Valid NaN-boxed n-bit
values therefore appear as negative quiet NaNs (qNaNs) when viewed as any wider m-bit value,
n <m FLEN.

Therefore, fmv.w.x should be used instead of fmv.d.x.

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