This project used the following tools:
- MyHDL/Python
- Mojo V3 - Xilinx Spartan 6 FPGA
- Logisim
- GTKWave
- Espresso
- Icarus Verilog
- madebyevan FSM Designer
Here are some materials that summarize the work:
| Name | Name | Last commit date | ||
|---|---|---|---|---|
This project used the following tools:
Here are some materials that summarize the work: