fix(esp32c3): correct -march to rv32imc to prevent illegal instruction crashes

internal/crosscompile/compile/rtlib/compiler_rt.go

@@ -11,13 +11,17 @@ import (
 func platformSpecifiedFiles(builtinsDir, target string) []string {
 	switch {
 	case strings.Contains(target, "riscv32"):
-		return []string{
+		files := []string{
 			filepath.Join(builtinsDir, "riscv", "mulsi3.S"),
 			filepath.Join(builtinsDir, "riscv", "fp_mode.c"),
 			filepath.Join(builtinsDir, "riscv", "save.S"),
 			filepath.Join(builtinsDir, "riscv", "restore.S"),
-			filepath.Join(builtinsDir, "atomic.c"),
 		}
+		// Only add atomic.c for non-ESP targets (ESP doesn't support A extension)
+		if target != "riscv32-esp-elf" {
+			files = append(files, filepath.Join(builtinsDir, "atomic.c"))
+		}
+		return files
 	case strings.Contains(target, "riscv64"):
 		return []string{
 			filepath.Join(builtinsDir, "addtf3.c"),

internal/crosscompile/crosscompile.go

@@ -531,7 +531,15 @@ func UseTarget(targetName string) (export Export, err error) {
 		// double.
 		ccflags = append(ccflags, "-mdouble=64")
 	case "riscv32":
-		ccflags = append(ccflags, "-march=rv32imac", "-fforce-enable-int128")
+		// Check llvm-target to distinguish ESP RISC-V chips from others
+		// ESP series (riscv32-esp-elf) only supports RV32IMC (no A/D/F extensions)
+		// Other RISC-V32 targets support RV32IMAC (with A extension)
+		if config.LLVMTarget == "riscv32-esp-elf" {
+			ccflags = append(ccflags, "-march=rv32imc")
+		} else {
+			ccflags = append(ccflags, "-march=rv32imac")
+		}
+		ccflags = append(ccflags, "-fforce-enable-int128")
 	case "riscv64":
 		ccflags = append(ccflags, "-march=rv64gc")
 	case "mips":

internal/crosscompile/crosscompile_test.go

@@ -175,6 +175,7 @@ func TestUseTarget(t *testing.T) {
 		expectError bool
 		expectLLVM  string
 		expectCPU   string
+		expectMarch string
 	}{
 		// FIXME(MeteorsLiu): wasi in useTarget
 		// {
@@ -205,6 +206,22 @@ func TestUseTarget(t *testing.T) {
 			expectLLVM:  "avr",
 			expectCPU:   "atmega328p",
 		},
+		{
+			name:        "RISC-V32 Target (generic)",
+			targetName:  "riscv32",
+			expectError: false,
+			expectLLVM:  "riscv32-unknown-none",
+			expectCPU:   "generic-rv32",
+			expectMarch: "-march=rv32imac", // Generic RISC-V32 uses rv32imac (with A extension)
+		},
+		{
+			name:        "ESP32-C3 Target (ESP RISC-V)",
+			targetName:  "esp32c3",
+			expectError: false,
+			expectLLVM:  "riscv32-esp-elf",
+			expectCPU:   "generic-rv32",
+			expectMarch: "-march=rv32imc", // ESP32-C3 uses rv32imc (no A extension)
+		},
 		{
 			name:        "Nonexistent Target",
 			targetName:  "nonexistent-target",
@@ -272,6 +289,20 @@ func TestUseTarget(t *testing.T) {
 				}
 			}
 
+			// Check if -march flag is correct
+			if tc.expectMarch != "" {
+				found := false
+				for _, flag := range export.CCFLAGS {
+					if flag == tc.expectMarch {
+						found = true
+						break
+					}
+				}
+				if !found {
+					t.Errorf("Expected %s in CCFLAGS, got %v", tc.expectMarch, export.CCFLAGS)
+				}
+			}
+
 			t.Logf("Target %s: BuildTags=%v, CFlags=%v, CCFlags=%v, LDFlags=%v",
 				tc.targetName, export.BuildTags, export.CFLAGS, export.CCFLAGS, export.LDFLAGS)
 		})

targets/esp32c3.json

@@ -1,6 +1,6 @@
 {
 	"inherits": [
-		"riscv32-nostart"
+		"riscv32-esp"
 	],
 	"features": "+32bit,+c,+m,+zmmul,-a,-b,-d,-e,-experimental-smmpm,-experimental-smnpm,-experimental-ssnpm,-experimental-sspm,-experimental-ssqosid,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-f,-h,-relax,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-v,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xesppie,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecdiscarddlone,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zicsr,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-ztso,-zvbb,-zvbc,-zve32f,-zve32x,-zve64d,-zve64f,-zve64x,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl128b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl32b,-zvl4096b,-zvl512b,-zvl64b,-zvl65536b,-zvl8192b",
 	"build-tags": [
@@ -10,9 +10,6 @@
 	"serial": "usb",
 	"rtlib": "compiler-rt",
 	"libc": "newlib-esp32",
-	"cflags": [
-		"-march=rv32imc"
-	],
 	"linkerscript": "targets/esp32c3.memory.ld",
 	"extra-files": [],
 	"binary-format": "esp32c3",

targets/riscv32-nostart.json → targets/riscv32-esp.json

@@ -1,13 +1,13 @@
 {
 	"inherits": ["riscv-nostart"],
-	"llvm-target": "riscv32-unknown-none",
+	"llvm-target": "riscv32-esp-elf",
 	"cpu": "generic-rv32",
 	"target-abi": "ilp32",
 	"build-tags": ["tinygo.riscv32"],
 	"scheduler": "tasks",
 	"default-stack-size": 2048,
 	"cflags": [
-		"-march=rv32imac"
+		"-march=rv32imc"
 	],
 	"ldflags": [
 		"-melf32lriscv"