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47 changes: 35 additions & 12 deletions src/MBC3.md
Original file line number Diff line number Diff line change
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# MBC3

(max 2MByte ROM and/or 32KByte RAM and Timer)
(max 4 MiB ROM, 64 KiB RAM, and timer)

Beside for the ability to access up to 2MB ROM (128 banks), and 32KB RAM
(4 banks), the MBC3 also includes a built-in Real Time Clock (RTC). The
RTC requires an external 32.768 kHz Quartz Oscillator, and an external
battery (if it should continue to tick when the Game Boy is turned off).
Beside for the ability to access up to 4 MiB ROM (256 banks) and 64 KiB RAM
(8 banks), the MBC3 also includes a built-in Real Time Clock (RTC), sometimes referred to as the timer. The
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The only place I've seen it referred to as the timer is in this file. Adding the alternative terminology makes it less clear what it is, which is an RTC.

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Both Pan Docs and RGBLINK exclusively use "timer". Only this file uses RTC. This is because it isn't a real-time clock as it cannot tell you the date. It has the days past since a certain period in time. It's simply a persistent timer. Using the hours, minutes, seconds counter as a clock is simply a feature that could be added easily.

RTC requires an external 32.768 kHz quartz crystal oscillator, and an external
battery (if it should continue to tick when the Game Boy is turned off). All official MBC3 releases utilize cartridge RAM and a battery, but a few DMG games don't use the timer and therefore lack the crystal.

There are (at least) four different versions of this MBC that can be distinguished by the print on the chip itself: MBC3, MBC3A, MBC3B and MBC30. Only the latter supports the full 4 MiB of ROM and 64 KiB of RAM whereas the other three can only access half of that. The MBC30 is only found in the Japanese _Pocket Monsters: Crystal Version_, which is also the only release with the full 64 KiB of RAM (8 banks). No game uses the full 4 MiB.

The different versions of the chip are not distinguished in the cartridge header, not even the MBC30.

## Memory

Expand Down Expand Up @@ -58,11 +62,25 @@ Controls what is mapped into memory at A000-BFFF.

### 6000-7FFF - Latch Clock Data (Write Only)

When writing $00, and then $01 to this register, the current time
becomes latched into the RTC registers. The latched data will not change
until it becomes latched again, by repeating the write $00-\>$01
procedure. This provides a way to read the RTC registers while the
clock keeps ticking.
Latching makes a static copy of the current timestamp available in the clock counter registers while the clock keeps running in the background. This makes sure that your reads from the counter registers will be consistent, since any counter overflowing while you read the different parts can have you read an incorrect value (e.g. reading the minute at 11:59 and the hour at 12:00 will give 12:59.)
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These sections should start with the basic technical information about the register itself.

  • what the register does -- controls the RTC register latch
  • the register interface / how to use it technically -- write value with bit 0 set/clear

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Latching is a rather technical term. I felt that it was more appropriate to describe this first, instead of writing "The latch clock data register can latch clock data." as the first sentence.
If you read on, you will notice that it has no universal behavior, just that writing an even value followed by an odd value will happen to work.

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I did not and would not suggest including "The latch clock data register can latch clock data." as the first (or any) sentence. You can see what I suggested should be the first thing in the section in my comment above.

I understood what you wrote and I did read the whole thing before choosing to submit the review including this comment.

I agree that an explanation of the purpose of the latching feature is necessary. But I don't think that should be the first thing under this heading.

(Like all the other comments, the relevant line here is the bottom one. The three above came for free.)


The exact behavior of this register varies depending on hardware:

MBC3B provides a running clock on power-on and after writing any even value to this register. It is still recommended to latch the clock by writing any odd value. MBC3B can only latch while it provides a running clock, so you must write an even value before you can write an odd value again.
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I don't think the two versions of this chip are mentioned before this point? I'd suggest adding a paragraph explaining this in the intro section.

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@CasualPokePlayer CasualPokePlayer Nov 17, 2025

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There are at least 4 versions of the chip to be clear: MBC3, MBC3A, MBC3B, and MBC30. Only MBC3A and MBC3B have been tested for latching quirks (so far).


MBC3A's clock counters are indeterminate by default. Writing any value to this register latches the clock. MBC3A cannot provide a running clock. Naturally, it can latch repeatedly.
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Unclear what "indeterminate by default" means here.

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What exactly do you not understand?

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The exact thing that I don't understand is the intended meaning of the phrase "indeterminate by default".

The text could be improved by plainly describing the behaviour that this phrase presumably refers to.

e.g. questions that could be answered:

  • What is the default state? RTC selected / Clock battery inserted / System power cycle?
  • What happens when you read from the registers?
  • What about writes?

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@nummacway nummacway Nov 19, 2025

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"What is the default state? RTC selected / Clock battery inserted / System power cycle?" - Power-cycle, but I didn't want to repeat the same word again.
"What happens when you read from the registers?" The clock counter registers are indeterminate.
"What about writes?" As clearly explained a few paragraphs further down, latching is optional for writes. Since this register is only used for latching on MBC3A, this means that you can write.

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Thanks for the explanation.
Specifically for this instance, I'd prefer to have the repetition. Using a different term to refer to the same thing suggests a difference in meaning.

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I believe we use expressions such as "These registers are left entirely uninitialized" instead of 'indeterminate'

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It's probably worth explaining the behaviour more specifically rather than relying on the phrase "latches the clock" which seems to use "latch" in an unusual way.
It sounds like a write to the register triggers an automatic sequence in which the latch is disabled and then enabled.

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For your first remark: That behaviour was just described two paragraphs above.
For the second one: What exactly are you referring to? You selected two full paragraphs.


**tl;dr:** Write $00 then $01 to this register to safely trigger latching on all versions of the chip.
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The usage of "tl;dr" does not match the style of the document.
Also, this is basic information and should be at the top of the section.

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Agree with @quinnyo here

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It seems that all of my comments in the review ended up pointing at more lines than what I anchored them to.
The line I was referring to here was only the "tl;dr" one at the bottom, in case that wasn't clear.

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I actually didn't want to change it for the same reason, but I did it anyway because it was requested by one of the primary maintainers.


:::tip

**Help wanted**

The exact latching behavior of MBC3 and MBC30 has not been tested and the sample size could be improved even for the MBC3A and MBC3B.

If you would like to help, have a flashcart and any official RTC cartridge, please reach out to us on gbdev Discord so you can be given the test ROMs.

:::

### Clock Counter Registers
| Register | Name | Description | Range |
Expand All @@ -73,8 +91,13 @@ clock keeps ticking.
| $0B | RTC DL | Lower 8 bits of Day Counter | ($00-$FF) |
| $0C | RTC DH | Upper 1 bit of Day Counter, Carry Bit, Halt Flag. <br>Bit 0: Most significant bit (Bit 8) of Day Counter<br>Bit 6: Halt (0=Active, 1=Stop Timer)<br>Bit 7: Day Counter Carry Bit (1=Counter Overflow) | |

The Halt Flag is supposed to be set before **writing** to the RTC
Registers.
The Halt Flag is supposed to be set before **writing** to the RTC Registers. This makes sure no register overflows while you write the different parts. The MBC3 chip however does not require you to halt or latch the clock before you write to the counter registers. Note that latching also prevents you from seeing your writes reflected immediately.

Bits that are not required to store the above information will be ignored and always read 0.

You can write values larger than the ones mentioned above (up to 63 for seconds and minutes, and up to 31 for hours). Invalid values will then continue incrementing like a valid value and will only overflow once the available bits no longer suffice. This overflow however will not cause a carry, neither does writing 60 or 24 directly. For example, if you write 30:59:63 (and clear the Halt Flag), it will be 30:59:00 one second later, and 31:00:00 one minute after that.

Writing to the seconds register also resets the inaccessible sub-second counter.

### The Day Counter

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