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refactor: refactoring cuda code to cute-dsl (part 1)#2428

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yzh119 wants to merge 17 commits intoflashinfer-ai:mainfrom
yzh119:cute-dsl-part-1
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refactor: refactoring cuda code to cute-dsl (part 1)#2428
yzh119 wants to merge 17 commits intoflashinfer-ai:mainfrom
yzh119:cute-dsl-part-1

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@yzh119
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@yzh119 yzh119 commented Jan 28, 2026

📌 Description

We prioritize using dsl for kernel development over cuda for faster JIT compilation speed.
This PR is the first series that refactors the simple normalization kernels to cute-dsl.

CUDA code should be ready to remove after we finish end-to-end testing.

🔍 Related Issues

🚀 Pull Request Checklist

Thank you for contributing to FlashInfer! Before we review your pull request, please make sure the following items are complete.

✅ Pre-commit Checks

  • I have installed pre-commit by running pip install pre-commit (or used your preferred method).
  • I have installed the hooks with pre-commit install.
  • I have run the hooks manually with pre-commit run --all-files and fixed any reported issues.

If you are unsure about how to set up pre-commit, see the pre-commit documentation.

🧪 Tests

  • Tests have been added or updated as needed.
  • All tests are passing (unittest, etc.).

Reviewer Notes

Summary by CodeRabbit

  • New Features

    • CuTe-DSL–accelerated normalization: RMSNorm (2D/3D), LayerNorm, fused add+RMSNorm, and FP8-quantized variants exposed for runtime use.
    • Shared norm utilities and JIT warmup to improve kernel readiness.
  • Chores

    • Runtime selection and fallback for CuTe-DSL/CUDA normalization with a visibility check.
  • Bug Fixes

    • Safer optional-dependency handling to avoid hard failures when CUDA/CuTe-DSL is unavailable.

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Summary of Changes

Hello @yzh119, I'm Gemini Code Assist1! I'm currently reviewing this pull request and will post my feedback shortly. In the meantime, here's a summary to help you and other reviewers quickly get up to speed!

This pull request marks the initial phase of refactoring the project's normalization kernels to leverage CuTe-DSL, aiming to enhance JIT compilation speed and overall kernel performance. It introduces a comprehensive set of CuTe-DSL-based normalization kernels and integrates them into the existing API with a conditional dispatch mechanism, paving the way for more efficient GPU computations.

Highlights

  • Introduction of CuTe-DSL Kernels: A new module flashinfer/cute_dsl/norm.py has been added, introducing several normalization kernels implemented using NVIDIA's CuTe-DSL. This includes RMSNormKernel, QKRMSNormKernel (for 3D tensors), RMSNormQuantKernel (with FP8 quantization), FusedAddRMSNormKernel, FusedAddRMSNormQuantKernel, and LayerNormKernel.
  • Conditional Kernel Dispatch: The existing flashinfer/norm.py has been updated to conditionally dispatch normalization operations to either the legacy CUDA JIT implementations or the new CuTe-DSL kernels. This is controlled by the FLASHINFER_USE_CUDA_NORM environment variable, allowing for a gradual transition and fallback mechanism.
  • Enhanced Normalization Functionality: The new CuTe-DSL kernels provide optimized implementations for various normalization types, including standard RMSNorm, RMSNorm with FP8 quantization, fused add operations, and LayerNorm. The QKRMSNormKernel specifically addresses 3D tensors with arbitrary strides, improving flexibility.
  • Low-Level Optimizations: The CuTe-DSL implementations incorporate low-level optimizations such as 128-bit vectorized loads, two-stage warp/block reductions, and direct PTX intrinsics for operations like fast reciprocal, min/max, and single-byte FP8 conversion/storage, ensuring high performance and numerical stability.

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📝 Walkthrough

Walkthrough

Adds CuTe-DSL normalization kernels (RMSNorm, QK RMSNorm, FP8-quantized and fused variants, LayerNorm), new norm utilities, and runtime dispatch between CUDA-JIT and CuTe-DSL; conditions imports/exports on CuTe-DSL availability and adjusts some TVM-FFI host-call argument representations.

Changes

Cohort / File(s) Summary
CuTe-DSL package
flashinfer/cute_dsl/__init__.py
Re-export norm kernel classes and API functions from flashinfer.norm.kernels behind is_cute_dsl_available(); extend __all__.
Top-level exports
flashinfer/__init__.py
Wrap rmsnorm_fp4quant / add_rmsnorm_fp4quant imports in try/except and catch ImportError/AttributeError to avoid hard failures when CuTe-DSL is missing.
Norm package entry
flashinfer/norm/__init__.py
Add FLASHINFER_USE_CUDA_NORM flag and dispatch logic: always import gen_norm_module (CUDA JIT warmup) and choose between CUDA-JIT vs CuTe-DSL implementations; rename internal helpers and expose __all__ for public norm APIs.
Norm kernels package init
flashinfer/norm/kernels/__init__.py
New initializer re-exporting CuTe-DSL kernel classes and Python APIs for RMSNorm, QKRMSNorm, RMSNormQuant, FusedAddRMSNorm, FusedAddRMSNormQuant, and LayerNorm.
RMSNorm implementations
flashinfer/norm/kernels/rmsnorm.py
Add RMSNormKernel, QKRMSNormKernel, RMSNormQuantKernel, compiled-kernel factories, and Python APIs (rmsnorm_cute, qk_rmsnorm_cute, rmsnorm_quant_cute).
Fused Add + RMSNorm
flashinfer/norm/kernels/fused_add_rmsnorm.py
Add FusedAddRMSNormKernel, FusedAddRMSNormQuantKernel, compiled-kernel factories, and APIs (fused_add_rmsnorm_cute, fused_add_rmsnorm_quant_cute).
LayerNorm kernel
flashinfer/norm/kernels/layernorm.py
Add LayerNormKernel, TVM-FFI compiled-kernel factory, and layernorm_cute API with tiled/shared-memory implementation.
Norm utilities
flashinfer/norm/utils.py
New utilities: FP8 constants & conversion, PTX intrinsics, warp/block reductions, predicate helpers, vector/thread helpers, layout builder, dtype-to-string conversion; re-export cutlass utils; add __all__.
CuTe-DSL host-call tweaks
flashinfer/cute_dsl/add_rmsnorm_fp4quant.py, flashinfer/cute_dsl/rmsnorm_fp4quant.py
Change TVM-FFI host-call invocation to pass plain Python int/float for scalar args (remove Int32(...) / Float32(...) wrappers).

Sequence Diagram(s)

sequenceDiagram
    participant App as Application
    participant NormAPI as flashinfer.norm
    participant Dispatcher as Dispatcher
    participant CUDAJIT as CUDA JIT (gen_norm_module)
    participant CuTeDSL as CuTe-DSL Path
    participant Compiled as Compiled Kernel (TVM/ptx)
    participant GPU as GPU Device

    App->>NormAPI: call rmsnorm(...)
    NormAPI->>Dispatcher: check FLASHINFER_USE_CUDA_NORM / is_cute_dsl_available()
    alt CUDA JIT selected
        Dispatcher->>CUDAJIT: request/jit module
        CUDAJIT->>Compiled: produce kernel
        Compiled->>GPU: execute kernel
    else CuTe-DSL selected
        Dispatcher->>CuTeDSL: request compiled CuTe kernel
        CuTeDSL->>Compiled: produce kernel (TVM-FFI)
        Compiled->>GPU: execute kernel
    end
    GPU-->>Compiled: result
    Compiled-->>NormAPI: output tensor
    NormAPI-->>App: return
Loading

Estimated code review effort

🎯 4 (Complex) | ⏱️ ~60 minutes

Possibly related PRs

Suggested labels

run-ci

Suggested reviewers

  • kaixih
  • aleozlx
  • bkryu
  • jimmyzho
  • nvmbreughe

Poem

🐰 I hopped through tiles and shared-memory nooks,
I threaded warps and peeked in kernel books.
CuTe or CUDA, I choose which way to run —
Norms now dance on GPUs, bright as the sun. ✨

🚥 Pre-merge checks | ✅ 2 | ❌ 1

❌ Failed checks (1 warning)

Check name Status Explanation Resolution
Docstring Coverage ⚠️ Warning Docstring coverage is 56.69% which is insufficient. The required threshold is 80.00%. Write docstrings for the functions missing them to satisfy the coverage threshold.
✅ Passed checks (2 passed)
Check name Status Explanation
Title check ✅ Passed The PR title accurately captures the main change: refactoring CUDA normalization kernels to CuTe-DSL implementation, which is the primary objective documented in the PR description and objectives.
Description check ✅ Passed The PR description covers the key intent (prioritizing DSL for faster JIT compilation), identifies this as part 1 of a series, notes CUDA code will be removed after testing, and indicates tests are passing. While pre-commit checklist items are not fully marked, the description provides sufficient context for the changes.

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@yzh119
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yzh119 commented Jan 28, 2026

/bot run

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Code Review

This pull request is a significant refactoring effort, moving normalization kernels from a custom CUDA JIT implementation to the CuTe-DSL. This is a commendable step towards improving performance and maintainability. The new flashinfer/cute_dsl/norm.py file is extensive and well-structured. My review has identified a few critical and high-severity issues that need to be addressed, including a bug in the FP8 quantization logic, incorrect API parameter naming, and inefficient shared memory usage. Once these issues are resolved, this will be a solid improvement.

.reg .b16 fp8_pair;
.reg .f32 zero;
mov.f32 zero, 0f00000000;
cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $0;
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critical

There is a bug in the PTX inline assembly. The cvt.rn.satfinite.e4m3x2.f32 instruction converts the second source operand and stores it in the upper half of the destination register. The st.global.b8 instruction then stores the lower 8 bits of the register. As written, this will store the converted zero value, not the intended val ($0).

To fix this, you should swap the source operands in the cvt instruction to place the converted value in the lower half of the fp8_pair register.

Suggested change
cvt.rn.satfinite.e4m3x2.f32 fp8_pair, zero, $0;
cvt.rn.satfinite.e4m3x2.f32 fp8_pair, $0, zero;

Comment on lines +1391 to +1393
self.cols_per_tile_f32 * 4 * 2
+ self.cols_per_tile * elem_bytes * 2
+ 2 * self.num_warps * 4
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high

The shared memory calculation for LayerNormKernel includes space for gamma/beta in the input dtype, but these shared memory tiles (sGamma, sBeta) are allocated and partitioned but never actually used in the kernel. The kernel reads gamma and beta values directly from the float32 shared memory tiles (sGamma_f32, sBeta_f32).

This wastes a significant amount of shared memory, which can negatively impact performance by reducing occupancy.

You should remove the allocation of sGamma and sBeta (lines 1483-1492) and their partitioning (lines 1565-1566) in the kernel method, and update this shared memory size calculation.

Suggested change
self.cols_per_tile_f32 * 4 * 2
+ self.cols_per_tile * elem_bytes * 2
+ 2 * self.num_warps * 4
self.cols_per_tile_f32 * 4 * 2
+ 2 * self.num_warps * 4

Comment on lines +1770 to +1787
def tensor_api(
input: torch.Tensor,
weight: torch.Tensor,
output: torch.Tensor,
B: int,
N: int,
eps: float,
num_blocks: int,
) -> None:
compiled_kernel(
input,
weight,
output,
Int32(B),
Int32(N),
Float32(eps),
Int32(num_blocks),
)
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high

The enable_pdl parameter is not being passed to the compiled kernel. The qk_rmsnorm_cute function accepts enable_pdl, but it's lost because the tensor_api wrapper doesn't accept it and pass it to the compiled_kernel call.

This is a bug that prevents Programmatic Dependent Launch from being used with this kernel. You should update tensor_api to accept enable_pdl and pass it through. You'll also need to update the call to kernel in qk_rmsnorm_cute (line 2087) to pass this new argument.

Suggested change
def tensor_api(
input: torch.Tensor,
weight: torch.Tensor,
output: torch.Tensor,
B: int,
N: int,
eps: float,
num_blocks: int,
) -> None:
compiled_kernel(
input,
weight,
output,
Int32(B),
Int32(N),
Float32(eps),
Int32(num_blocks),
)
def tensor_api(
input: torch.Tensor,
weight: torch.Tensor,
output: torch.Tensor,
B: int,
N: int,
eps: float,
enable_pdl: bool,
num_blocks: int,
) -> None:
compiled_kernel(
input,
weight,
output,
Int32(B),
Int32(N),
Float32(eps),
enable_pdl,
Int32(num_blocks),
)

Comment on lines +231 to +253
def predicate_k_3d(tXcX: cute.Tensor, limit: int) -> cute.Tensor:
"""Create predicate tensor for bounds checking (3D tensors).

For 3D tensors after local_tile, the last coordinate [2] is the head_dim dimension.
"""
tXpX = cute.make_rmem_tensor(
cute.make_layout(
(
cute.size(tXcX, mode=[0, 1]),
cute.size(tXcX, mode=[1]),
cute.size(tXcX, mode=[2]),
),
stride=(cute.size(tXcX, mode=[2]), 0, 1),
),
cutlass.Boolean,
)
for rest_v in cutlass.range_constexpr(tXpX.shape[0]):
for rest_k in cutlass.range_constexpr(tXpX.shape[2]):
# For 3D tensor, coordinate[2] is the head_dim index
tXpX[rest_v, 0, rest_k] = cute.elem_less(
tXcX[(0, rest_v), 0, rest_k][2], limit
)
return tXpX
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medium

The function predicate_k_3d is defined but does not appear to be used anywhere in the new code. It seems to be dead code and should be removed to improve code clarity and maintainability.


idX = cute.make_identity_tensor(mX.shape)
gX = cute.local_tile(mX, tiler_mn, (bidx, 0))
cute.local_tile(mY, tiler_mn, (bidx, 0))
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medium

The result of this cute.local_tile call is not used, so this line has no effect and can be removed. A similar unused call exists in FusedAddRMSNormQuantKernel.kernel on line 1233.

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GitLab MR !272 has been created, and the CI pipeline #42732703 is currently running. I'll report back once the pipeline job completes.

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Actionable comments posted: 1

🤖 Fix all issues with AI agents
In `@flashinfer/cute_dsl/norm.py`:
- Around line 2044-2088: The qk_rmsnorm_cute function accepts enable_pdl but
never forwards it to the kernel compilation (kernel created via
_get_compiled_qk_rmsnorm_kernel uses a hardcoded value); update qk_rmsnorm_cute
to pass the enable_pdl flag into _get_compiled_qk_rmsnorm_kernel (or else remove
enable_pdl from qk_rmsnorm_cute's signature) so the compiled kernel respects PDL
support — locate the _get_compiled_qk_rmsnorm_kernel call in qk_rmsnorm_cute and
change its arguments to include enable_pdl (and ensure any downstream kernel
invocation/signature matches this added parameter).
🧹 Nitpick comments (8)
flashinfer/cute_dsl/norm.py (8)

858-862: Dead code: cute.local_tile(mY, ...) result is unused.

The result of cute.local_tile(mY, tiler_mn, (bidx, 0)) at line 860 is not assigned to a variable. The FP8 output is stored using PTX scalar stores later (lines 920-922), which access mY directly with computed offsets. This call appears to be unnecessary.

♻️ Proposed fix
         idX = cute.make_identity_tensor(mX.shape)
         gX = cute.local_tile(mX, tiler_mn, (bidx, 0))
-        cute.local_tile(mY, tiler_mn, (bidx, 0))
         cX = cute.local_tile(idX, tiler_mn, (bidx, 0))

1231-1236: Same issue: cute.local_tile(mY, ...) result is unused.

Same dead code pattern as in RMSNormQuantKernel.

♻️ Proposed fix
         idX = cute.make_identity_tensor(mX.shape)

-        cute.local_tile(mY, tiler_mn, (bidx, 0))
         gX = cute.local_tile(mX, tiler_mn, (bidx, 0))
         gR = cute.local_tile(mR, tiler_mn, (bidx, 0))
         cX = cute.local_tile(idX, tiler_mn, (bidx, 0))

1564-1567: Dead code: partition_D results are unused.

The results of thr_copy_load.partition_D(sGamma) and thr_copy_load.partition_D(sBeta) are not assigned to variables. Gamma/beta are loaded directly from sGamma_f32/sBeta_f32 at lines 1634-1635.

♻️ Proposed fix
-        # Partitions for gamma/beta (input dtype)
-        thr_copy_load.partition_D(sGamma)
-        thr_copy_load.partition_D(sBeta)
-
         # Register fragments - initialize to zero for proper handling of out-of-bounds threads

2016-2042: Missing @flashinfer_api decorator on public API function.

The rmsnorm_cute function is exported in __all__ and thus part of the public API, but it lacks the @flashinfer_api decorator required by coding guidelines.

Additionally, the enable_pdl parameter is accepted but completely ignored. The kernel is compiled with a hardcoded False value at line 1764. This breaks the API contract with callers who expect PDL to be honored.

♻️ Proposed fix for decorator
+from ..api_logging import flashinfer_api
+
+@flashinfer_api
 def rmsnorm_cute(
     input: torch.Tensor,

As per coding guidelines: "Use @flashinfer_api decorator for debugging API calls."


2090-2113: Same issues: missing @flashinfer_api decorator and unused enable_pdl.

rmsnorm_quant_cute has the same issues as rmsnorm_cute.


2116-2135: Same issues: missing @flashinfer_api decorator and unused enable_pdl.

fused_add_rmsnorm_cute has the same issues.


2138-2170: Same issues: missing @flashinfer_api decorator and unused enable_pdl.

fused_add_rmsnorm_quant_cute has the same issues.


2173-2192: Missing @flashinfer_api decorator.

layernorm_cute is missing the @flashinfer_api decorator. Note that this function doesn't have an enable_pdl parameter, which is consistent since it doesn't expose PDL functionality.

Comment on lines +2044 to +2088
def qk_rmsnorm_cute(
input: torch.Tensor,
weight: torch.Tensor,
output: torch.Tensor,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
"""CuTe DSL QKRMSNorm for 3D tensors [batch, heads, head_dim].

Supports arbitrary stride - no need to call contiguous().
Each warp processes one (batch, head) pair independently using warp-only reduction.

Args:
input: Input tensor of shape [batch_size, num_heads, head_dim].
Last dimension must be contiguous (stride[-1] == 1).
weight: Weight tensor of shape [head_dim].
output: Output tensor (same shape as input).
eps: Small constant for numerical stability.
weight_bias: Bias added to weight (0 for standard RMSNorm, 1 for Gemma).
enable_pdl: Enable Programmatic Dependent Launch for SM90+ GPUs.
"""
assert input.dim() == 3, "QKRMSNorm expects 3D input [batch, heads, head_dim]"

batch_size, num_heads, head_dim = input.shape
M = batch_size * num_heads

# Kernel configuration
num_warps = 4

# Calculate grid size based on SM count and estimated occupancy
num_sms = get_num_sm(input.device)
blocks_per_sm = 16 # Theoretical max for 128-thread blocks
max_blocks = num_sms * blocks_per_sm
needed_blocks = (M + num_warps - 1) // num_warps
num_blocks = min(max_blocks, needed_blocks)

dtype_str = _torch_dtype_to_str(input.dtype)
kernel = _get_compiled_qk_rmsnorm_kernel(
dtype_str, head_dim, weight_bias, num_warps
)

# Pass 3D tensors directly - kernel handles arbitrary stride
kernel(input, weight, output, batch_size, num_heads, eps, num_blocks)

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⚠️ Potential issue | 🟡 Minor

enable_pdl parameter is accepted but not effectively used.

The qk_rmsnorm_cute function accepts enable_pdl but the compiled kernel at line 1764 uses a hardcoded enable_pdl=False. The kernel supports PDL (lines 617-618, 747-748), but the parameter isn't being passed through during compilation.

🔧 Proposed fix to support PDL

To properly support PDL, the compilation would need to be done at runtime with the actual enable_pdl value, or the parameter should be removed from the API signature if PDL is intentionally disabled for CuTe-DSL kernels.

If PDL is intentionally disabled, consider removing the parameter:

 def qk_rmsnorm_cute(
     input: torch.Tensor,
     weight: torch.Tensor,
     output: torch.Tensor,
     eps: float = 1e-6,
     weight_bias: float = 0.0,
-    enable_pdl: bool = False,
 ) -> None:
📝 Committable suggestion

‼️ IMPORTANT
Carefully review the code before committing. Ensure that it accurately replaces the highlighted code, contains no missing lines, and has no issues with indentation. Thoroughly test & benchmark the code to ensure it meets the requirements.

Suggested change
def qk_rmsnorm_cute(
input: torch.Tensor,
weight: torch.Tensor,
output: torch.Tensor,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
"""CuTe DSL QKRMSNorm for 3D tensors [batch, heads, head_dim].
Supports arbitrary stride - no need to call contiguous().
Each warp processes one (batch, head) pair independently using warp-only reduction.
Args:
input: Input tensor of shape [batch_size, num_heads, head_dim].
Last dimension must be contiguous (stride[-1] == 1).
weight: Weight tensor of shape [head_dim].
output: Output tensor (same shape as input).
eps: Small constant for numerical stability.
weight_bias: Bias added to weight (0 for standard RMSNorm, 1 for Gemma).
enable_pdl: Enable Programmatic Dependent Launch for SM90+ GPUs.
"""
assert input.dim() == 3, "QKRMSNorm expects 3D input [batch, heads, head_dim]"
batch_size, num_heads, head_dim = input.shape
M = batch_size * num_heads
# Kernel configuration
num_warps = 4
# Calculate grid size based on SM count and estimated occupancy
num_sms = get_num_sm(input.device)
blocks_per_sm = 16 # Theoretical max for 128-thread blocks
max_blocks = num_sms * blocks_per_sm
needed_blocks = (M + num_warps - 1) // num_warps
num_blocks = min(max_blocks, needed_blocks)
dtype_str = _torch_dtype_to_str(input.dtype)
kernel = _get_compiled_qk_rmsnorm_kernel(
dtype_str, head_dim, weight_bias, num_warps
)
# Pass 3D tensors directly - kernel handles arbitrary stride
kernel(input, weight, output, batch_size, num_heads, eps, num_blocks)
def qk_rmsnorm_cute(
input: torch.Tensor,
weight: torch.Tensor,
output: torch.Tensor,
eps: float = 1e-6,
weight_bias: float = 0.0,
) -> None:
"""CuTe DSL QKRMSNorm for 3D tensors [batch, heads, head_dim].
Supports arbitrary stride - no need to call contiguous().
Each warp processes one (batch, head) pair independently using warp-only reduction.
Args:
input: Input tensor of shape [batch_size, num_heads, head_dim].
Last dimension must be contiguous (stride[-1] == 1).
weight: Weight tensor of shape [head_dim].
output: Output tensor (same shape as input).
eps: Small constant for numerical stability.
weight_bias: Bias added to weight (0 for standard RMSNorm, 1 for Gemma).
"""
assert input.dim() == 3, "QKRMSNorm expects 3D input [batch, heads, head_dim]"
batch_size, num_heads, head_dim = input.shape
M = batch_size * num_heads
# Kernel configuration
num_warps = 4
# Calculate grid size based on SM count and estimated occupancy
num_sms = get_num_sm(input.device)
blocks_per_sm = 16 # Theoretical max for 128-thread blocks
max_blocks = num_sms * blocks_per_sm
needed_blocks = (M + num_warps - 1) // num_warps
num_blocks = min(max_blocks, needed_blocks)
dtype_str = _torch_dtype_to_str(input.dtype)
kernel = _get_compiled_qk_rmsnorm_kernel(
dtype_str, head_dim, weight_bias, num_warps
)
# Pass 3D tensors directly - kernel handles arbitrary stride
kernel(input, weight, output, batch_size, num_heads, eps, num_blocks)
🧰 Tools
🪛 Ruff (0.14.14)

2050-2050: Unused function argument: enable_pdl

(ARG001)

🤖 Prompt for AI Agents
In `@flashinfer/cute_dsl/norm.py` around lines 2044 - 2088, The qk_rmsnorm_cute
function accepts enable_pdl but never forwards it to the kernel compilation
(kernel created via _get_compiled_qk_rmsnorm_kernel uses a hardcoded value);
update qk_rmsnorm_cute to pass the enable_pdl flag into
_get_compiled_qk_rmsnorm_kernel (or else remove enable_pdl from
qk_rmsnorm_cute's signature) so the compiled kernel respects PDL support —
locate the _get_compiled_qk_rmsnorm_kernel call in qk_rmsnorm_cute and change
its arguments to include enable_pdl (and ensure any downstream kernel
invocation/signature matches this added parameter).

@flashinfer-bot
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[FAILED] Pipeline #42732703: 1/20 passed

@yzh119
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yzh119 commented Jan 28, 2026

/bot run

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GitLab MR !272 has been updated with latest changes, and the CI pipeline #42752005 is currently running. I'll report back once the pipeline job completes.

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Actionable comments posted: 5

🤖 Fix all issues with AI agents
In `@flashinfer/cute_dsl/norm.py`:
- Around line 1875-1882: The parameter enable_pdl in rmsnorm_cute is unused and
triggers ARG001; explicitly mark it as intentionally unused by adding a no-op
assignment (e.g., _ = enable_pdl) or a targeted noqa comment inside rmsnorm_cute
to show API-parity intent, and apply the same change to the other wrapper
functions mentioned in the review so each unused enable_pdl is acknowledged
rather than left unused.
- Around line 1875-2051: The public CuTe-DSL wrapper functions (rmsnorm_cute,
qk_rmsnorm_cute, rmsnorm_quant_cute, fused_add_rmsnorm_cute,
fused_add_rmsnorm_quant_cute, layernorm_cute) need the `@flashinfer_api` decorator
added and the decorator imported from the project’s standard utilities; add a
single import for flashinfer_api near other imports and prepend `@flashinfer_api`
above each of these function definitions so all public entry points are traced
for API-call logging (keep existing signatures and bodies unchanged).
- Around line 371-379: Rename the unused kernel parameter M to _M in the kernel
signatures to silence Ruff ARG002 (e.g., change the argument name in
cute_dsl.norm.LayerNormKernel.kernel and the other flagged kernels
RMSNormQuantKernel.kernel, FusedAddRMSNormKernel.kernel,
FusedAddRMSNormQuantKernel.kernel); update the parameter name only in the
function signature (or alternatively add a targeted "# noqa: ARG002" comment) so
the intent is clear and linters stop reporting the unused argument.
- Around line 1188-1200: The scalar FP8 store computes out_offset assuming
row-major contiguous layout (out_offset = bidx * H + idx), which fails for
non-contiguous mY; update the store in the block that calls
cvt_and_store_f32_to_e4m3/get_ptr_as_int64 to compute the correct linear offset
using the output tensor's stride (e.g., out_offset = bidx * mY.stride[0] + idx)
or mirror the non-quantized kernels by using CuTe's local_tile/partition_D logic
(as in FusedAddRMSNormKernel) to derive the physical address; ensure you
reference mY.stride and preserve idx calculation so cvt_and_store_f32_to_e4m3
receives the correct out_ptr for any layout.
- Around line 835-847: The FP8 store currently computes out_offset as bidx * H +
idx which assumes a contiguous row stride; update the offset calculation to use
the actual row stride (sym_row_stride_y) so stores respect arbitrary output
tensor strides—replace the use of H in out_offset with sym_row_stride_y (i.e.,
compute out_offset = bidx * sym_row_stride_y + idx) in the block that calls
get_ptr_as_int64(mY, Int32(out_offset)) and cvt_and_store_f32_to_e4m3; ensure
any alternative tiled layout approach mirrors how inputs are handled so the
store remains stride-aware.

Comment on lines +371 to +379
def kernel(
self,
mX: cute.Tensor,
mW: cute.Tensor,
mY: cute.Tensor,
M: Int32,
eps: Float32,
tv_layout: cute.Layout,
tiler_mn: cute.Shape,
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⚠️ Potential issue | 🟡 Minor

Silence unused M kernel args to keep Ruff clean.

Ruff reports ARG002 for M in kernel signatures. Since M is not used inside kernels, rename it to _M (or add a targeted # noqa: ARG002) to document intent and satisfy lint. Apply the same pattern to the other kernel methods flagged by Ruff (RMSNormQuantKernel.kernel, FusedAddRMSNormKernel.kernel, FusedAddRMSNormQuantKernel.kernel, LayerNormKernel.kernel).

♻️ Example fix (apply similarly to other kernels)
-        M: Int32,
+        _M: Int32,
🧰 Tools
🪛 Ruff (0.14.14)

376-376: Unused method argument: M

(ARG002)

🤖 Prompt for AI Agents
In `@flashinfer/cute_dsl/norm.py` around lines 371 - 379, Rename the unused kernel
parameter M to _M in the kernel signatures to silence Ruff ARG002 (e.g., change
the argument name in cute_dsl.norm.LayerNormKernel.kernel and the other flagged
kernels RMSNormQuantKernel.kernel, FusedAddRMSNormKernel.kernel,
FusedAddRMSNormQuantKernel.kernel); update the parameter name only in the
function signature (or alternatively add a targeted "# noqa: ARG002" comment) so
the intent is clear and linters stop reporting the unused argument.

Comment on lines +835 to +847
col_offset = tidx * vec_size
for v in cutlass.range_constexpr(num_vec_blocks):
for e in cutlass.range_constexpr(vec_size):
idx = col_offset + v * threads_per_row * vec_size + e
if idx < H:
# Clamp and convert - use flat index for register tensor
flat_idx = v * vec_size + e
clamped = max(tYrY_f32[flat_idx], Float32(-FLOAT8_E4M3_MAX))
clamped = min(clamped, Float32(FLOAT8_E4M3_MAX))
# Use PTX to convert and store FP8 byte
out_offset = bidx * H + idx
out_ptr = get_ptr_as_int64(mY, Int32(out_offset))
cvt_and_store_f32_to_e4m3(clamped, out_ptr)
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⚠️ Potential issue | 🟠 Major

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Use stride-aware offset calculation for FP8 output store.

Line 96: out_offset = bidx * H + idx assumes contiguous row stride equal to H, which breaks for arbitrary-stride outputs declared in the tensor layout (stride = sym_row_stride_y). Replace with out_offset = bidx * sym_row_stride_y + idx, or apply consistent tiled layout to the output tensor (as done for input) to automatically respect strides.

🤖 Prompt for AI Agents
In `@flashinfer/cute_dsl/norm.py` around lines 835 - 847, The FP8 store currently
computes out_offset as bidx * H + idx which assumes a contiguous row stride;
update the offset calculation to use the actual row stride (sym_row_stride_y) so
stores respect arbitrary output tensor strides—replace the use of H in
out_offset with sym_row_stride_y (i.e., compute out_offset = bidx *
sym_row_stride_y + idx) in the block that calls get_ptr_as_int64(mY,
Int32(out_offset)) and cvt_and_store_f32_to_e4m3; ensure any alternative tiled
layout approach mirrors how inputs are handled so the store remains
stride-aware.

Comment on lines +1188 to +1200
col_offset = tidx * vec_size
for v in cutlass.range_constexpr(num_vec_blocks):
for e in cutlass.range_constexpr(vec_size):
idx = col_offset + v * threads_per_row * vec_size + e
if idx < H:
# Clamp and convert - use flat index for register tensor
flat_idx = v * vec_size + e
clamped = max(tYrY_f32[flat_idx], Float32(-FLOAT8_E4M3_MAX))
clamped = min(clamped, Float32(FLOAT8_E4M3_MAX))
# Use PTX to convert and store FP8 byte
out_offset = bidx * H + idx
out_ptr = get_ptr_as_int64(mY, Int32(out_offset))
cvt_and_store_f32_to_e4m3(clamped, out_ptr)
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⚠️ Potential issue | 🟠 Major

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The FP8 scalar store path assumes row-major contiguous output layout.

The hardcoded out_offset = bidx * H + idx breaks non-contiguous outputs. Use CuTe's local_tile and partition_D like the non-quantized kernels (e.g., FusedAddRMSNormKernel), or query the output tensor's stride and compute out_offset = bidx * mY.stride[0] + idx.

🤖 Prompt for AI Agents
In `@flashinfer/cute_dsl/norm.py` around lines 1188 - 1200, The scalar FP8 store
computes out_offset assuming row-major contiguous layout (out_offset = bidx * H
+ idx), which fails for non-contiguous mY; update the store in the block that
calls cvt_and_store_f32_to_e4m3/get_ptr_as_int64 to compute the correct linear
offset using the output tensor's stride (e.g., out_offset = bidx * mY.stride[0]
+ idx) or mirror the non-quantized kernels by using CuTe's
local_tile/partition_D logic (as in FusedAddRMSNormKernel) to derive the
physical address; ensure you reference mY.stride and preserve idx calculation so
cvt_and_store_f32_to_e4m3 receives the correct out_ptr for any layout.

Comment on lines +1875 to +1882
def rmsnorm_cute(
input: torch.Tensor,
weight: torch.Tensor,
out: torch.Tensor,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
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⚠️ Potential issue | 🟡 Minor

enable_pdl is unused in most wrappers.

Ruff flags ARG001 for these functions. If the parameter is only for API parity, make the intent explicit (e.g., _ = enable_pdl or a targeted # noqa: ARG001). Otherwise, plumb it through once those kernels support PDL.

✅ Example (apply similarly to other wrappers)
 def rmsnorm_cute(
     input: torch.Tensor,
     weight: torch.Tensor,
     out: torch.Tensor,
     eps: float = 1e-6,
     weight_bias: float = 0.0,
     enable_pdl: bool = False,
 ) -> None:
+    _ = enable_pdl  # reserved for future PDL support
     """CuTe DSL RMSNorm implementation.

Also applies to: 1949-1957, 1975-1982, 1997-2006

🧰 Tools
🪛 Ruff (0.14.14)

1881-1881: Unused function argument: enable_pdl

(ARG001)

🤖 Prompt for AI Agents
In `@flashinfer/cute_dsl/norm.py` around lines 1875 - 1882, The parameter
enable_pdl in rmsnorm_cute is unused and triggers ARG001; explicitly mark it as
intentionally unused by adding a no-op assignment (e.g., _ = enable_pdl) or a
targeted noqa comment inside rmsnorm_cute to show API-parity intent, and apply
the same change to the other wrapper functions mentioned in the review so each
unused enable_pdl is acknowledged rather than left unused.

Comment on lines +1875 to +2051
def rmsnorm_cute(
input: torch.Tensor,
weight: torch.Tensor,
out: torch.Tensor,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
"""CuTe DSL RMSNorm implementation.

Supports arbitrary stride - no need to call contiguous().
Last dimension must be contiguous (stride[-1] == 1).
"""
H = input.shape[-1]
if input.dim() == 3:
M = input.shape[0] * input.shape[1]
input_2d = input.view(M, H)
out_2d = out.view(M, H)
else:
M = input.shape[0]
input_2d = input
out_2d = out

dtype_str = _torch_dtype_to_str(input.dtype)
kernel = _get_compiled_rmsnorm_kernel(dtype_str, H, weight_bias)
kernel(input_2d, weight, out_2d, M, eps)


def qk_rmsnorm_cute(
input: torch.Tensor,
weight: torch.Tensor,
output: torch.Tensor,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
"""CuTe DSL QKRMSNorm for 3D tensors [batch, heads, head_dim].

Supports arbitrary stride - no need to call contiguous().
Each warp processes one (batch, head) pair independently using warp-only reduction.

Args:
input: Input tensor of shape [batch_size, num_heads, head_dim].
Last dimension must be contiguous (stride[-1] == 1).
weight: Weight tensor of shape [head_dim].
output: Output tensor (same shape as input).
eps: Small constant for numerical stability.
weight_bias: Bias added to weight (0 for standard RMSNorm, 1 for Gemma).
enable_pdl: Enable Programmatic Dependent Launch for SM90+ GPUs.
"""
assert input.dim() == 3, "QKRMSNorm expects 3D input [batch, heads, head_dim]"

batch_size, num_heads, head_dim = input.shape
M = batch_size * num_heads

# Kernel configuration
num_warps = 4

# Calculate grid size based on SM count and estimated occupancy
num_sms = get_num_sm(input.device)
blocks_per_sm = 16 # Theoretical max for 128-thread blocks
max_blocks = num_sms * blocks_per_sm
needed_blocks = (M + num_warps - 1) // num_warps
num_blocks = min(max_blocks, needed_blocks)

dtype_str = _torch_dtype_to_str(input.dtype)
kernel = _get_compiled_qk_rmsnorm_kernel(
dtype_str, head_dim, weight_bias, num_warps
)

# Pass 3D tensors directly - kernel handles arbitrary stride
kernel(input, weight, output, batch_size, num_heads, eps, num_blocks)


def rmsnorm_quant_cute(
out: torch.Tensor,
input: torch.Tensor,
weight: torch.Tensor,
scale: float,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
"""CuTe DSL RMSNorm + FP8 quantization implementation.

Supports arbitrary stride - no need to call contiguous().
Last dimension must be contiguous (stride[-1] == 1).
"""

H = input.shape[-1]
M = input.shape[0]

dtype_str = _torch_dtype_to_str(input.dtype)
out_dtype_str = _torch_dtype_to_str(out.dtype)
kernel = _get_compiled_rmsnorm_quant_kernel(
dtype_str, out_dtype_str, H, weight_bias
)
kernel(out, input, weight, M, scale, eps)


def fused_add_rmsnorm_cute(
input: torch.Tensor,
residual: torch.Tensor,
weight: torch.Tensor,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
"""CuTe DSL Fused Add + RMSNorm implementation.

Supports arbitrary stride - no need to call contiguous().
Last dimension must be contiguous (stride[-1] == 1).
"""

H = input.shape[-1]
M = input.shape[0]

dtype_str = _torch_dtype_to_str(input.dtype)
kernel = _get_compiled_fused_add_rmsnorm_kernel(dtype_str, H, weight_bias)
kernel(input, residual, weight, M, eps)


def fused_add_rmsnorm_quant_cute(
out: torch.Tensor,
input: torch.Tensor,
residual: torch.Tensor,
weight: torch.Tensor,
scale: float,
eps: float = 1e-6,
weight_bias: float = 0.0,
enable_pdl: bool = False,
) -> None:
"""CuTe DSL Fused Add + RMSNorm + FP8 quantization implementation.

Supports arbitrary stride - no need to call contiguous().
Last dimension must be contiguous (stride[-1] == 1).
"""

H = input.shape[-1]
M = input.shape[0]

dtype_str = _torch_dtype_to_str(input.dtype)
out_dtype_str = _torch_dtype_to_str(out.dtype)
kernel = _get_compiled_fused_add_rmsnorm_quant_kernel(
dtype_str, out_dtype_str, H, weight_bias
)
kernel(
out,
input,
residual,
weight,
M,
scale,
eps,
)


def layernorm_cute(
out: torch.Tensor,
input: torch.Tensor,
gamma: torch.Tensor,
beta: torch.Tensor,
eps: float = 1e-6,
) -> None:
"""CuTe DSL LayerNorm implementation.

Supports arbitrary stride - no need to call contiguous().
Last dimension must be contiguous (stride[-1] == 1).
"""

H = input.shape[-1]
M = input.shape[0]

dtype_str = _torch_dtype_to_str(input.dtype)
gamma_dtype_str = _torch_dtype_to_str(gamma.dtype)
kernel = _get_compiled_layernorm_kernel(dtype_str, gamma_dtype_str, H)
kernel(out, input, gamma, beta, M, eps)
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🛠️ Refactor suggestion | 🟠 Major

Add @flashinfer_api on public CuTe-DSL API wrappers.

The public Python entry points here (e.g., rmsnorm_cute, qk_rmsnorm_cute, rmsnorm_quant_cute, fused_add_rmsnorm_cute, fused_add_rmsnorm_quant_cute, layernorm_cute) should be decorated for API-call tracing. Please apply @flashinfer_api (and import it from the standard location used elsewhere in the repo).

As per coding guidelines: Use @flashinfer_api decorator for debugging API calls, enable via FLASHINFER_LOGLEVEL environment variable (0=off, 1=basic, 3=detailed, 5=with stats).

🧰 Tools
🪛 Ruff (0.14.14)

1881-1881: Unused function argument: enable_pdl

(ARG001)


1909-1909: Unused function argument: enable_pdl

(ARG001)


1956-1956: Unused function argument: enable_pdl

(ARG001)


1981-1981: Unused function argument: enable_pdl

(ARG001)


2005-2005: Unused function argument: enable_pdl

(ARG001)

🤖 Prompt for AI Agents
In `@flashinfer/cute_dsl/norm.py` around lines 1875 - 2051, The public CuTe-DSL
wrapper functions (rmsnorm_cute, qk_rmsnorm_cute, rmsnorm_quant_cute,
fused_add_rmsnorm_cute, fused_add_rmsnorm_quant_cute, layernorm_cute) need the
`@flashinfer_api` decorator added and the decorator imported from the project’s
standard utilities; add a single import for flashinfer_api near other imports
and prepend `@flashinfer_api` above each of these function definitions so all
public entry points are traced for API-call logging (keep existing signatures
and bodies unchanged).

@bkryu
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bkryu commented Jan 28, 2026

Hi @yzh119, is this a translation of the existing norm kernels from CUDA to CuTe DSL? or is it a re-write for better performance?

Asking because I'm curious whether it resolves #2396

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Actionable comments posted: 1

🤖 Fix all issues with AI agents
In `@flashinfer/norm.py`:
- Around line 468-471: The unconditional imports of rmsnorm_fp4quant and
add_rmsnorm_fp4quant from .cute_dsl can raise when cutlass/cute_dsl isn't
available; wrap these imports in a try/except (or check
cute_dsl.is_cute_dsl_available()) and fall back to setting rmsnorm_fp4quant =
None and add_rmsnorm_fp4quant = None so the module can still import and the
existing _USE_CUDA_NORM/CUDA fallback logic can decide at runtime; update any
usage sites to handle None accordingly.

Comment on lines +468 to +471
# CuTe-DSL fused RMSNorm + FP4 Quantization kernels
# These require CuTe-DSL to be available and SM100+ (Blackwell) GPUs
try:
from .cute_dsl import rmsnorm_fp4quant, add_rmsnorm_fp4quant
except ImportError:
# CuTe-DSL not available
rmsnorm_fp4quant = None # type: ignore[misc,assignment]
add_rmsnorm_fp4quant = None # type: ignore[misc,assignment]
# These require SM100+ (Blackwell) GPUs
from .cute_dsl import rmsnorm_fp4quant as rmsnorm_fp4quant
from .cute_dsl import add_rmsnorm_fp4quant as add_rmsnorm_fp4quant
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⚠️ Potential issue | 🟠 Major

🧩 Analysis chain

🏁 Script executed:

# First, let's look at the actual file structure around lines 468-471 in flashinfer/norm.py
head -n 480 flashinfer/norm.py | tail -n 30

Repository: flashinfer-ai/flashinfer

Length of output: 914


🏁 Script executed:

# Also check if there's a _USE_CUDA_NORM conditional block and where these imports sit relative to it
rg -n "_USE_CUDA_NORM|SM100|Blackwell" flashinfer/norm.py -A 5 -B 5

Repository: flashinfer-ai/flashinfer

Length of output: 4119


🏁 Script executed:

# Search for existing error handling patterns with cute_dsl imports elsewhere
rg -n "cute_dsl|try.*import|except ImportError" flashinfer/ --type py -l

Repository: flashinfer-ai/flashinfer

Length of output: 439


🏁 Script executed:

# Check how the cute_dsl module is structured and whether it handles SM100+ checks
head -n 100 flashinfer/cute_dsl.py 2>/dev/null || find . -name "cute_dsl*" -type f

Repository: flashinfer-ai/flashinfer

Length of output: 50


🏁 Script executed:

# Check the cute_dsl __init__.py to see if there's SM100 version checking
cat -n flashinfer/cute_dsl/__init__.py

Repository: flashinfer-ai/flashinfer

Length of output: 3281


🏁 Script executed:

# Search for rmsnorm_fp4quant definition and any SM100 guards
rg -n "rmsnorm_fp4quant|SM100" flashinfer/cute_dsl/ --type py -B 3 -A 3

Repository: flashinfer-ai/flashinfer

Length of output: 11099


🏁 Script executed:

# Check if cute_dsl module raises errors or handles gracefully on non-SM100 systems
rg -n "raise|RuntimeError|ImportError|version|compute_capability" flashinfer/cute_dsl/ --type py

Repository: flashinfer-ai/flashinfer

Length of output: 6658


🏁 Script executed:

# Check how the module is used after import - are these functions wrapped with SM100 checks?
rg -n "rmsnorm_fp4quant\|add_rmsnorm_fp4quant" flashinfer/ --type py -B 2 -A 5

Repository: flashinfer-ai/flashinfer

Length of output: 50


🏁 Script executed:

# Find the is_cute_dsl_available function
rg -n "def is_cute_dsl_available" flashinfer/ --type py -A 10

Repository: flashinfer-ai/flashinfer

Length of output: 742


🏁 Script executed:

# Check the utils.py in cute_dsl to see what is_cute_dsl_available does
head -n 50 flashinfer/cute_dsl/utils.py

Repository: flashinfer-ai/flashinfer

Length of output: 1524


🏁 Script executed:

# Check how rmsnorm_fp4quant and add_rmsnorm_fp4quant are used after import
rg -n "rmsnorm_fp4quant|add_rmsnorm_fp4quant" flashinfer/norm.py -A 3 -B 3

Repository: flashinfer-ai/flashinfer

Length of output: 306


🏁 Script executed:

# Also check if there's any __getattr__ or dynamic import fallback in norm.py or at module level
rg -n "__getattr__|try:|except|__all__" flashinfer/norm.py | head -20

Repository: flashinfer-ai/flashinfer

Length of output: 134


🏁 Script executed:

# Check flashinfer's main __init__.py to see if norm module import is conditional
head -n 100 flashinfer/__init__.py

Repository: flashinfer-ai/flashinfer

Length of output: 3782


Wrap FP4 imports in try/except to prevent import failures on systems without cutlass.

The rmsnorm_fp4quant and add_rmsnorm_fp4quant imports are unconditional, but cute_dsl/__init__.py only exports them when is_cute_dsl_available() returns True (i.e., when cutlass is installed). Without error handling, importing flashinfer.norm will fail on systems without cutlass, even though the module provides CUDA-based fallbacks via _USE_CUDA_NORM. This breaks backward compatibility.

Suggested pattern for graceful degradation
 # CuTe-DSL fused RMSNorm + FP4 Quantization kernels
 # These require SM100+ (Blackwell) GPUs
-from .cute_dsl import rmsnorm_fp4quant as rmsnorm_fp4quant
-from .cute_dsl import add_rmsnorm_fp4quant as add_rmsnorm_fp4quant
+try:
+    from .cute_dsl import rmsnorm_fp4quant as rmsnorm_fp4quant
+    from .cute_dsl import add_rmsnorm_fp4quant as add_rmsnorm_fp4quant
+except ImportError:
+    rmsnorm_fp4quant = None
+    add_rmsnorm_fp4quant = None
🤖 Prompt for AI Agents
In `@flashinfer/norm.py` around lines 468 - 471, The unconditional imports of
rmsnorm_fp4quant and add_rmsnorm_fp4quant from .cute_dsl can raise when
cutlass/cute_dsl isn't available; wrap these imports in a try/except (or check
cute_dsl.is_cute_dsl_available()) and fall back to setting rmsnorm_fp4quant =
None and add_rmsnorm_fp4quant = None so the module can still import and the
existing _USE_CUDA_NORM/CUDA fallback logic can decide at runtime; update any
usage sites to handle None accordingly.

@aleozlx
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aleozlx commented Jan 28, 2026

wanna ask you @yzh119 about the reason we put these things all in cute_dsl
would it be a good idea we put the kernels in the cute_dsl folder into different ops in the future? because i feel organizing them by ops feel more understandable and the language is a next level detail

@yzh119
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yzh119 commented Jan 28, 2026

would it be a good idea we put the kernels in the cute_dsl folder into different ops in the future? because i feel organizing them by ops feel more understandable and the language is a next level detail

We should categorize kernels by functionalities, not sources. All kernels inside cute_dsl should be refactored, we can do that in another PR.

For this specific PR, let me make norm a module and move cute-dsl code under this folder.

@bkryu
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bkryu commented Jan 28, 2026

cc @kahyunnam

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[CANCELED] Pipeline #42752005: canceled

@kahyunnam
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I found some cpu overhead which makes the host+device execution time slower than cuda's implementation (even though cute-dsl kernel is faster). @cyx-6 is investigating whether we are using tvm-ffi correctly.

I suggest holding on until we fix the CPU overhead.

@yzh119 @cyx-6 were there any updates for this tvm-ffi investigation? (Just curious, since I was also working on a cute-dsl implementation of RoPE)

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♻️ Duplicate comments (5)
flashinfer/norm/kernels/rmsnorm.py (2)

871-877: ⚠️ Potential issue | 🔴 Critical

Fix runtime argument order in rmsnorm_quant_cute.

Line 876 passes (out, input, weight, ...), but the compiled kernel expects (input, weight, out, ...). This can produce invalid reads/writes or immediate failure.

Suggested fix
-    kernel(out, input, weight, M, scale, eps)
+    kernel(input, weight, out, M, scale, eps)
🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@flashinfer/norm/kernels/rmsnorm.py` around lines 871 - 877, The runtime call
to the compiled kernel uses the wrong argument order: change the kernel
invocation in rmsnorm_quant_cute (where kernel is obtained via
_get_compiled_rmsnorm_quant_kernel) from kernel(out, input, weight, M, scale,
eps) to kernel(input, weight, out, M, scale, eps) so the compiled kernel
receives (input, weight, out, ...) as expected and avoids invalid reads/writes.

562-564: ⚠️ Potential issue | 🟠 Major

FP8 quant store still assumes contiguous output rows.

Line 619 computes bidx * H + idx, which ignores output row stride and breaks non-contiguous output tensors.

Suggested fix
         idX = cute.make_identity_tensor(mX.shape)
         gX = cute.local_tile(mX, tiler_mn, (bidx, 0))
+        gY = cute.local_tile(mY, tiler_mn, (bidx, 0))
         cX = cute.local_tile(idX, tiler_mn, (bidx, 0))
@@
-                    out_offset = bidx * H + idx
-                    out_ptr = get_ptr_as_int64(mY, Int32(out_offset))
+                    out_ptr = get_ptr_as_int64(gY, Int32(idx))
                     cvt_and_store_f32_to_e4m3(clamped, out_ptr)

Also applies to: 619-621

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@flashinfer/norm/kernels/rmsnorm.py` around lines 562 - 564, The FP8 quant
store logic assumes contiguous output rows by computing global row index as bidx
* H + idx (breaking for non-contiguous outputs); update the index computation to
use the actual output row stride instead of H and use the tensor's stride/shape
information when creating identity and local tiles (references: idX from
cute.make_identity_tensor, gX/cX from cute.local_tile, and the bidx/idx
calculations). Replace any hard-coded H multipliers with a derived row_stride
(or call that returns the logical row offset) so gX/cX and the FP8 store address
calculations work with non-contiguous output tensors. Ensure the same change is
applied at the other occurrence noted (lines 619–621).
flashinfer/norm/kernels/layernorm.py (2)

366-372: ⚠️ Potential issue | 🟠 Major

gamma_dtype_str is accepted in the compile path but not honored by the kernel.

Line 370 parses gamma_dtype, but Line 371 constructs LayerNormKernel(dtype, H) and the kernel data path is fixed to Float32 gamma/beta. Non-fp32 gamma/beta inputs can break behavior.

Minimal safety fix (enforce fp32 gamma/beta at API boundary)
 def layernorm_cute(
@@
-    dtype_str = _torch_dtype_to_str(input.dtype)
-    gamma_dtype_str = _torch_dtype_to_str(gamma.dtype)
-    kernel = _get_compiled_layernorm_kernel(dtype_str, gamma_dtype_str, H, enable_pdl)
+    dtype_str = _torch_dtype_to_str(input.dtype)
+    if gamma.dtype != torch.float32 or beta.dtype != torch.float32:
+        raise TypeError(
+            "layernorm_cute currently requires gamma/beta to be torch.float32"
+        )
+    kernel = _get_compiled_layernorm_kernel(dtype_str, "float32", H, enable_pdl)

Also applies to: 431-434

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@flashinfer/norm/kernels/layernorm.py` around lines 366 - 372, The function is
parsing gamma_dtype_str but not using it—LayerNormKernel is being constructed
with only dtype and H so gamma/beta are forced to fp32; update the compile path
to propagate gamma_dtype into the kernel creation or enforce fp32 at the API
boundary. Specifically, change the call that constructs LayerNormKernel(dtype,
H) to include the parsed gamma_dtype (e.g., LayerNormKernel(dtype, gamma_dtype,
H) or equivalent constructor) and update the LayerNormKernel
constructor/signature to accept and store gamma/beta dtype, or alternatively
validate gamma_dtype_str early and raise/convert to fp32 before proceeding;
repeat the same fix for the second occurrence around the other compile path
where gamma_dtype_str is parsed (the similar block at the other reported
location).

90-100: ⚠️ Potential issue | 🟠 Major

Remove dead gamma/beta scratch allocations to cut SMEM pressure.

Lines 196-206 and Lines 270-279 allocate/partition sGamma/sBeta and tXrGamma/tXrBeta, but they are never read. Line 90 still accounts for this unused footprint.

Suggested cleanup
     def _smem_size_in_bytes(self) -> int:
-        # Shared memory for:
-        # - gamma/beta f32 tiles: cols_per_tile_f32 * 4 * 2
-        # - gamma/beta input dtype tiles: cols_per_tile * elem_bytes * 2
-        # - reduction buffers: 2 * num_warps * 4
-        elem_bytes = self.dtype.width // 8
-        return (
-            self.cols_per_tile_f32 * 4 * 2
-            + self.cols_per_tile * elem_bytes * 2
-            + 2 * self.num_warps * 4
-        )
+        # Shared memory for:
+        # - gamma/beta f32 tiles: cols_per_tile_f32 * 4 * 2
+        # - reduction buffers: 2 * num_warps * 4
+        return self.cols_per_tile_f32 * 4 * 2 + 2 * self.num_warps * 4
@@
-        # Shared memory tiles for gamma, beta in input dtype (for matching shape with x)
-        sGamma = smem.allocate_tensor(
-            mX.element_type,
-            cute.make_ordered_layout(tiler_mn, order=(1, 0)),
-            byte_alignment=16,
-        )
-        sBeta = smem.allocate_tensor(
-            mX.element_type,
-            cute.make_ordered_layout(tiler_mn, order=(1, 0)),
-            byte_alignment=16,
-        )
@@
-        # Partitions for gamma/beta (input dtype)
-        thr_copy_load.partition_D(sGamma)
-        thr_copy_load.partition_D(sBeta)
@@
-        tXrGamma = cute.make_rmem_tensor(tXgX.shape, mX.element_type)
-        tXrBeta = cute.make_rmem_tensor(tXgX.shape, mX.element_type)
         tXrX.store(cute.zeros_like(tXrX, dtype=mX.element_type))
-        tXrGamma.store(cute.zeros_like(tXrGamma, dtype=mX.element_type))
-        tXrBeta.store(cute.zeros_like(tXrBeta, dtype=mX.element_type))

Also applies to: 196-206, 270-279

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@flashinfer/norm/kernels/layernorm.py` around lines 90 - 100, The
shared-memory size calculation in _smem_size_in_bytes() is overstating required
SMEM because scratch allocations for sGamma/sBeta and tXrGamma/tXrBeta are never
used; remove those unused allocations and corresponding size from the
computation. Update _smem_size_in_bytes() to exclude the gamma/beta f32 and
input-dtype tile terms (the expressions using cols_per_tile_f32 and
cols_per_tile * elem_bytes) and adjust any code that partitions/allocates
sGamma, sBeta, tXrGamma, tXrBeta (remove those variables/partitions) so only the
actual reduction buffer space (2 * num_warps * 4) and any remaining live tiles
are accounted for. Ensure references to cols_per_tile_f32, cols_per_tile,
elem_bytes, and num_warps remain correct for the retained allocations.
flashinfer/norm/kernels/fused_add_rmsnorm.py (1)

339-341: ⚠️ Potential issue | 🟠 Major

Respect output row stride in the FP8 scalar store path.

Line 415 hardcodes contiguous-row addressing (bidx * H + idx). That breaks the arbitrary-stride contract for non-contiguous outputs.

Suggested fix
-        gX = cute.local_tile(mX, tiler_mn, (bidx, 0))
-        gR = cute.local_tile(mR, tiler_mn, (bidx, 0))
+        gX = cute.local_tile(mX, tiler_mn, (bidx, 0))
+        gR = cute.local_tile(mR, tiler_mn, (bidx, 0))
+        gY = cute.local_tile(mY, tiler_mn, (bidx, 0))
         cX = cute.local_tile(idX, tiler_mn, (bidx, 0))
@@
-                    out_offset = bidx * H + idx
-                    out_ptr = get_ptr_as_int64(mY, Int32(out_offset))
+                    out_ptr = get_ptr_as_int64(gY, Int32(idx))
                     cvt_and_store_f32_to_e4m3(clamped, out_ptr)

Also applies to: 415-417

🤖 Prompt for AI Agents
Verify each finding against the current code and only fix it if needed.

In `@flashinfer/norm/kernels/fused_add_rmsnorm.py` around lines 339 - 341, The FP8
scalar store path currently computes target element addresses using a hardcoded
contiguous-row formula (bidx * H + idx) which ignores arbitrary output row
strides; update the scalar store logic to use the output buffer's actual row
stride instead of H — derive the row stride from the tile/descriptor associated
with idX/cX (or use the same stride used when creating gX/gR/cX via
cute.local_tile/tiler_mn) and compute the base offset as bidx * out_row_stride +
idx; apply the same fix to the other occurrences in the FP8 path (the three
places corresponding to the contiguous address calculation).
🤖 Prompt for all review comments with AI agents
Verify each finding against the current code and only fix it if needed.

Duplicate comments:
In `@flashinfer/norm/kernels/fused_add_rmsnorm.py`:
- Around line 339-341: The FP8 scalar store path currently computes target
element addresses using a hardcoded contiguous-row formula (bidx * H + idx)
which ignores arbitrary output row strides; update the scalar store logic to use
the output buffer's actual row stride instead of H — derive the row stride from
the tile/descriptor associated with idX/cX (or use the same stride used when
creating gX/gR/cX via cute.local_tile/tiler_mn) and compute the base offset as
bidx * out_row_stride + idx; apply the same fix to the other occurrences in the
FP8 path (the three places corresponding to the contiguous address calculation).

In `@flashinfer/norm/kernels/layernorm.py`:
- Around line 366-372: The function is parsing gamma_dtype_str but not using
it—LayerNormKernel is being constructed with only dtype and H so gamma/beta are
forced to fp32; update the compile path to propagate gamma_dtype into the kernel
creation or enforce fp32 at the API boundary. Specifically, change the call that
constructs LayerNormKernel(dtype, H) to include the parsed gamma_dtype (e.g.,
LayerNormKernel(dtype, gamma_dtype, H) or equivalent constructor) and update the
LayerNormKernel constructor/signature to accept and store gamma/beta dtype, or
alternatively validate gamma_dtype_str early and raise/convert to fp32 before
proceeding; repeat the same fix for the second occurrence around the other
compile path where gamma_dtype_str is parsed (the similar block at the other
reported location).
- Around line 90-100: The shared-memory size calculation in
_smem_size_in_bytes() is overstating required SMEM because scratch allocations
for sGamma/sBeta and tXrGamma/tXrBeta are never used; remove those unused
allocations and corresponding size from the computation. Update
_smem_size_in_bytes() to exclude the gamma/beta f32 and input-dtype tile terms
(the expressions using cols_per_tile_f32 and cols_per_tile * elem_bytes) and
adjust any code that partitions/allocates sGamma, sBeta, tXrGamma, tXrBeta
(remove those variables/partitions) so only the actual reduction buffer space (2
* num_warps * 4) and any remaining live tiles are accounted for. Ensure
references to cols_per_tile_f32, cols_per_tile, elem_bytes, and num_warps remain
correct for the retained allocations.

In `@flashinfer/norm/kernels/rmsnorm.py`:
- Around line 871-877: The runtime call to the compiled kernel uses the wrong
argument order: change the kernel invocation in rmsnorm_quant_cute (where kernel
is obtained via _get_compiled_rmsnorm_quant_kernel) from kernel(out, input,
weight, M, scale, eps) to kernel(input, weight, out, M, scale, eps) so the
compiled kernel receives (input, weight, out, ...) as expected and avoids
invalid reads/writes.
- Around line 562-564: The FP8 quant store logic assumes contiguous output rows
by computing global row index as bidx * H + idx (breaking for non-contiguous
outputs); update the index computation to use the actual output row stride
instead of H and use the tensor's stride/shape information when creating
identity and local tiles (references: idX from cute.make_identity_tensor, gX/cX
from cute.local_tile, and the bidx/idx calculations). Replace any hard-coded H
multipliers with a derived row_stride (or call that returns the logical row
offset) so gX/cX and the FP8 store address calculations work with non-contiguous
output tensors. Ensure the same change is applied at the other occurrence noted
(lines 619–621).

ℹ️ Review info

Configuration used: defaults

Review profile: CHILL

Plan: Pro

📥 Commits

Reviewing files that changed from the base of the PR and between 510b6f6 and 11649ab.

📒 Files selected for processing (7)
  • flashinfer/__init__.py
  • flashinfer/cute_dsl/__init__.py
  • flashinfer/cute_dsl/add_rmsnorm_fp4quant.py
  • flashinfer/norm/kernels/fused_add_rmsnorm.py
  • flashinfer/norm/kernels/layernorm.py
  • flashinfer/norm/kernels/rmsnorm.py
  • flashinfer/norm/utils.py
🚧 Files skipped from review as they are similar to previous changes (2)
  • flashinfer/init.py
  • flashinfer/cute_dsl/add_rmsnorm_fp4quant.py

@bkryu
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bkryu commented Mar 2, 2026

/bot run

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GitLab MR !272 has been updated with latest changes, and the CI pipeline #45155756 is currently running. I'll report back once the pipeline job completes.

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[FAILED] Pipeline #45155756: 7/20 passed

@bkryu bkryu added the run-ci label Mar 2, 2026
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bkryu commented Mar 2, 2026

/bot run

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GitLab MR !272 has been updated with latest changes, and the CI pipeline #45179095 is currently running. I'll report back once the pipeline job completes.

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with reference to #2459, scale would need to be a tensor for it to be cuda graph compatible similar change would be required for rmsnorm_quant_cute also

@bkryu can this be addressed before merging as it blocks my sglang changes

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[CANCELING] Pipeline #45179095: canceled

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bkryu commented Mar 3, 2026

with reference to #2459, scale would need to be a tensor for it to be cuda graph compatible similar change would be required for rmsnorm_quant_cute also

@bkryu can this be addressed before merging as it blocks my sglang changes

Thanks @DevashishLal-CB. I absorbed #2459 in a newly added commit a7690ec by essentially bringing over all the changes. Is this what you were looking for?

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bkryu commented Mar 3, 2026

/bot run

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GitLab MR !272 has been updated with latest changes, and the CI pipeline #45268078 is currently running. I'll report back once the pipeline job completes.

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[CANCELING] Pipeline #45268078: canceled

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bkryu commented Mar 4, 2026

/bot run

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GitLab MR !272 has been created, and the CI pipeline #45342593 is currently running. I'll report back once the pipeline job completes.

@DevashishLal-CB
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with reference to #2459, scale would need to be a tensor for it to be cuda graph compatible similar change would be required for rmsnorm_quant_cute also

@bkryu can this be addressed before merging as it blocks my sglang changes

Thanks @DevashishLal-CB. I absorbed #2459 in a newly added commit a7690ec by essentially bringing over all the changes. Is this what you were looking for?

Yup thanks, LGTM!

@bkryu bkryu added the op: norm label Mar 4, 2026
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[SUCCESS] Pipeline #45342593: 10/20 passed

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7 participants