fix: Update x86/6.1 MSR baselines with RFDS_NO

CHANGELOG.md

@@ -24,6 +24,11 @@ and this project adheres to
   `--config` parameter of `cpu-template-helper` optional. Users no longer need
   to prepare kernel, rootfs and Firecracker configuration files to use
   `cpu-template-helper`.
+- [#4537](https://github.com/firecracker-microvm/firecracker/pull/4537) Changed
+  T2CL template to pass through bit 27 of `MSR_IA32_ARCH_CAPABILITIES`
+  (`RFDS_NO`).
+- [#4537](https://github.com/firecracker-microvm/firecracker/pull/4537) Changed
+  T2S template to set bit 27 of `MSR_IA32_ARCH_CAPABILITIES` (`RFDS_NO`) to 1.
 
 ### Deprecated
 

src/vmm/src/cpu_config/x86_64/static_cpu_templates/t2cl.rs

@@ -277,12 +277,13 @@ pub fn t2cl() -> CustomCpuTemplate {
             // - Bit 19: RRSBA
             // - Bit 24: PBRSB_NO
             // - Bit 26: GDS_NO
+            // - Bit 27: RFDS_NO
             //
             // Note that this MSR is specific to Intel processors.
             RegisterModifier {
                 addr: 0x10a,
                 bitmap: RegisterValueFilter {
-                    filter: 0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1010_1111_0101_0001_1110_0000_0000,
+                    filter: 0b1111_1111_1111_1111_1111_1111_1111_1111_1111_0010_1111_0101_0001_1110_0000_0000,
                     value: 0b0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000,
                 },
             },

src/vmm/src/cpu_config/x86_64/static_cpu_templates/t2s.rs

@@ -255,12 +255,13 @@ pub fn t2s() -> CustomCpuTemplate {
             // - Bit 23: OVERCLOCKING_STATUS
             // - Bit 24: PBRSB_NO
             // - Bit 26: GDS_NO
+            // - BIT 27: RFDS_NO
             // - Bits 63-25: Reserved
             RegisterModifier {
             addr: 0x10a,
             bitmap: RegisterValueFilter {
                 filter: 0b1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111_1111,
-                value: 0b0000_0000_0000_0000_0000_0000_0000_0000_0000_0100_0000_1000_0000_1100_0100_1100,
+                value: 0b0000_0000_0000_0000_0000_0000_0000_0000_0000_1100_0000_1000_0000_1100_0100_1100,
             },
         }],
         ..Default::default()

tests/data/cpu_template_helper/fingerprint_INTEL_CASCADELAKE_6.1host.json

@@ -1128,7 +1128,7 @@
       },
       {
         "addr": "0x10a",
-        "bitmap": "0b0000000000000000000000000000000000000100000010101010000011101011"
+        "bitmap": "0b0000000000000000000000000000000000001100000010101010000011101011"
       },
       {
         "addr": "0x140",

tests/data/cpu_template_helper/fingerprint_INTEL_ICELAKE_6.1host.json

@@ -1220,7 +1220,7 @@
       },
       {
         "addr": "0x10a",
-        "bitmap": "0b0000000000000000000000000000000000000100000000101010000011101011"
+        "bitmap": "0b0000000000000000000000000000000000001100000000101010000011101011"
       },
       {
         "addr": "0x140",

tests/data/cpu_template_helper/fingerprint_INTEL_SKYLAKE_6.1host.json

@@ -1128,7 +1128,7 @@
       },
       {
         "addr": "0x10a",
-        "bitmap": "0b0000000000000000000000000000000000000100000000000000000001001100"
+        "bitmap": "0b0000000000000000000000000000000000001100000000000000000001001100"
       },
       {
         "addr": "0x140",

tests/data/static_cpu_templates/t2cl.json

@@ -90,7 +90,7 @@
   "msr_modifiers": [
     {
       "addr": "0x10a",
-      "bitmap": "0b0000000000000000000000000000000000000x0x0000x0x0xxx0000xxxxxxxxx"
+      "bitmap": "0b000000000000000000000000000000000000xx0x0000x0x0xxx0000xxxxxxxxx"
     }
   ]
 }

tests/data/static_cpu_templates/t2s.json

@@ -90,7 +90,7 @@
   "msr_modifiers": [
     {
       "addr": "0x10a",
-      "bitmap": "0b0000000000000000000000000000000000000100000010000000110001001100"
+      "bitmap": "0b0000000000000000000000000000000000001100000010000000110001001100"
     }
   ]
 }