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Lowlevel LLVM-like language as HDL middle layer #19

@XVilka

Description

@XVilka

Basic idea is to create something low-level, like LLVM Bitcode or WebAssembly, to create the HDL compilers emit the code in this format, which will be fed to the routers/synthesizers after. This will allow to add 1) targets easier 2) HDL frontends easier.

Criteria for selection:

  • Do we expect it to have a human readable form? [BOTH]
    • binary version
      - a text version with extracted symbol table?
      - more tops per file?
      - Include?
  • behavioural description / pure structural? [STRUCTURAL]
    - process (Verilog like mux, reg... desc.) / netlist (mux, reg, ... descr. by instance) ?
    - is Chisel3 FIRRTL/Yosys RTLIL structural enough?
  • Do we want it to be technology independent? [YES]
  • Do we require parameters/preprocessor? [NO]
  • Granularity gate / operator / process?
  • Which has the priority in optimizations: loading time/analysis/modification/file size?
  • Support for tristate signals?
    - Support for strong/weak pull up/down?
  • Clock domain as a wrapper around part of the netlist/ only as a input clk to registers?
  • Support for synthesis related pragmas like multiclock path, clock domain crossing?

Needs of the particular projects:

Chisel3

  • netlist of statements (process without explicit sensitivity)?

HWT

  • netlist of statements

magma

  • netlist of statements

MyHDL

  • processes

SpinalHDL

  • netlist of statements

Veriloggen

  • whole Verilog

Yosys

  • netlist of hw processes ?

Updates from #19 (comment) and #19 (comment)

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