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Rename SizedFIFO modules in AXIGate, Controller to avoid some Vivado issues Use Smartconnect in place of Interconnect v2 (due to deprecation, missing Versal support) On Versal, use emb_mem_gen (Versal-only) in place of blk_mem_gen (7-series to UltraScale+). Allow disabling local memory (note: setting needs support in the specific core tcl) TODO: Set data_width, addr_width for each core, or find an alternative to retrieving DATA_WIDTH/ADDR_WIDTH from the interconnect master.
Set the advanced properties of the smartconnect ports: M00_Buffer AR_SIZE=4, etc. Retrieve data_width and addr_width directly from the core's memory interface, as Smartconnect is not evaluated immediately. Support BRAM_SIZE=0 in all cores (tested only CVA5,6 for now) -> Note: The user must manually set the core's reset PC to external memory. This setting now entirely prevents BRAM instantiation.
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Addresses some issues related to Versal (V80) with Vivado 2024.2.
Unrelated: Allow disabling local memory (note: will likely have to fix the reset/boot PC setting somewhere in the core's files)
For Versal boards, the Makefile variables PYNQ, TAPASCO_PLATFORM, VERSAL need to be set accordingly.