[API Implementation]: Support for Intel SHA extensions

src/coreclr/inc/clrconfigvalues.h

@@ -744,6 +744,7 @@ RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVX2,         W("EnableAVX2"),         1
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableAVXVNNI,      W("EnableAVXVNNI"),      1, "Allows AVX VNNI+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI1,         W("EnableBMI1"),         1, "Allows BMI1+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableBMI2,         W("EnableBMI2"),         1, "Allows BMI2+ hardware intrinsics to be disabled")
+RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableSHA,          W("EnableSHA"),          1, "Allows SHA+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableFMA,          W("EnableFMA"),          1, "Allows FMA+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnableLZCNT,        W("EnableLZCNT"),        1, "Allows LZCNT+ hardware intrinsics to be disabled")
 RETAIL_CONFIG_DWORD_INFO(EXTERNAL_EnablePCLMULQDQ,    W("EnablePCLMULQDQ"),    1, "Allows PCLMULQDQ+ hardware intrinsics to be disabled")

src/coreclr/inc/corinfoinstructionset.h

@@ -57,23 +57,25 @@ enum CORINFO_InstructionSet
     InstructionSet_Vector128=17,
     InstructionSet_Vector256=18,
     InstructionSet_AVXVNNI=19,
-    InstructionSet_X86Base_X64=20,
-    InstructionSet_SSE_X64=21,
-    InstructionSet_SSE2_X64=22,
-    InstructionSet_SSE3_X64=23,
-    InstructionSet_SSSE3_X64=24,
-    InstructionSet_SSE41_X64=25,
-    InstructionSet_SSE42_X64=26,
-    InstructionSet_AVX_X64=27,
-    InstructionSet_AVX2_X64=28,
-    InstructionSet_AES_X64=29,
-    InstructionSet_BMI1_X64=30,
-    InstructionSet_BMI2_X64=31,
-    InstructionSet_FMA_X64=32,
-    InstructionSet_LZCNT_X64=33,
-    InstructionSet_PCLMULQDQ_X64=34,
-    InstructionSet_POPCNT_X64=35,
-    InstructionSet_AVXVNNI_X64=36,
+    InstructionSet_SHA=20,
+    InstructionSet_X86Base_X64=21,
+    InstructionSet_SSE_X64=22,
+    InstructionSet_SSE2_X64=23,
+    InstructionSet_SSE3_X64=24,
+    InstructionSet_SSSE3_X64=25,
+    InstructionSet_SSE41_X64=26,
+    InstructionSet_SSE42_X64=27,
+    InstructionSet_AVX_X64=28,
+    InstructionSet_AVX2_X64=29,
+    InstructionSet_AES_X64=30,
+    InstructionSet_BMI1_X64=31,
+    InstructionSet_BMI2_X64=32,
+    InstructionSet_FMA_X64=33,
+    InstructionSet_LZCNT_X64=34,
+    InstructionSet_PCLMULQDQ_X64=35,
+    InstructionSet_POPCNT_X64=36,
+    InstructionSet_AVXVNNI_X64=37,
+    InstructionSet_SHA_X64=38,
 #endif // TARGET_AMD64
 #ifdef TARGET_X86
     InstructionSet_X86Base=1,
@@ -95,23 +97,25 @@ enum CORINFO_InstructionSet
     InstructionSet_Vector128=17,
     InstructionSet_Vector256=18,
     InstructionSet_AVXVNNI=19,
-    InstructionSet_X86Base_X64=20,
-    InstructionSet_SSE_X64=21,
-    InstructionSet_SSE2_X64=22,
-    InstructionSet_SSE3_X64=23,
-    InstructionSet_SSSE3_X64=24,
-    InstructionSet_SSE41_X64=25,
-    InstructionSet_SSE42_X64=26,
-    InstructionSet_AVX_X64=27,
-    InstructionSet_AVX2_X64=28,
-    InstructionSet_AES_X64=29,
-    InstructionSet_BMI1_X64=30,
-    InstructionSet_BMI2_X64=31,
-    InstructionSet_FMA_X64=32,
-    InstructionSet_LZCNT_X64=33,
-    InstructionSet_PCLMULQDQ_X64=34,
-    InstructionSet_POPCNT_X64=35,
-    InstructionSet_AVXVNNI_X64=36,
+    InstructionSet_SHA=20,
+    InstructionSet_X86Base_X64=21,
+    InstructionSet_SSE_X64=22,
+    InstructionSet_SSE2_X64=23,
+    InstructionSet_SSE3_X64=24,
+    InstructionSet_SSSE3_X64=25,
+    InstructionSet_SSE41_X64=26,
+    InstructionSet_SSE42_X64=27,
+    InstructionSet_AVX_X64=28,
+    InstructionSet_AVX2_X64=29,
+    InstructionSet_AES_X64=30,
+    InstructionSet_BMI1_X64=31,
+    InstructionSet_BMI2_X64=32,
+    InstructionSet_FMA_X64=33,
+    InstructionSet_LZCNT_X64=34,
+    InstructionSet_PCLMULQDQ_X64=35,
+    InstructionSet_POPCNT_X64=36,
+    InstructionSet_AVXVNNI_X64=37,
+    InstructionSet_SHA_X64=38,
 #endif // TARGET_X86
 
 };
@@ -211,6 +215,8 @@ struct CORINFO_InstructionSetFlags
             AddInstructionSet(InstructionSet_POPCNT_X64);
         if (HasInstructionSet(InstructionSet_AVXVNNI))
             AddInstructionSet(InstructionSet_AVXVNNI_X64);
+        if (HasInstructionSet(InstructionSet_SHA))
+            AddInstructionSet(InstructionSet_SHA_X64);
 #endif // TARGET_AMD64
 #ifdef TARGET_X86
 #endif // TARGET_X86
@@ -356,6 +362,10 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
             resultflags.RemoveInstructionSet(InstructionSet_AVXVNNI);
         if (resultflags.HasInstructionSet(InstructionSet_AVXVNNI_X64) && !resultflags.HasInstructionSet(InstructionSet_AVXVNNI))
             resultflags.RemoveInstructionSet(InstructionSet_AVXVNNI_X64);
+        if (resultflags.HasInstructionSet(InstructionSet_SHA) && !resultflags.HasInstructionSet(InstructionSet_SHA_X64))
+            resultflags.RemoveInstructionSet(InstructionSet_SHA);
+        if (resultflags.HasInstructionSet(InstructionSet_SHA_X64) && !resultflags.HasInstructionSet(InstructionSet_SHA))
+            resultflags.RemoveInstructionSet(InstructionSet_SHA_X64);
         if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
             resultflags.RemoveInstructionSet(InstructionSet_SSE);
         if (resultflags.HasInstructionSet(InstructionSet_SSE2) && !resultflags.HasInstructionSet(InstructionSet_SSE))
@@ -392,6 +402,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
             resultflags.RemoveInstructionSet(InstructionSet_Vector256);
         if (resultflags.HasInstructionSet(InstructionSet_AVXVNNI) && !resultflags.HasInstructionSet(InstructionSet_AVX2))
             resultflags.RemoveInstructionSet(InstructionSet_AVXVNNI);
+        if (resultflags.HasInstructionSet(InstructionSet_SHA) && !resultflags.HasInstructionSet(InstructionSet_SSE2))
+            resultflags.RemoveInstructionSet(InstructionSet_SHA);
 #endif // TARGET_AMD64
 #ifdef TARGET_X86
         if (resultflags.HasInstructionSet(InstructionSet_SSE) && !resultflags.HasInstructionSet(InstructionSet_X86Base))
@@ -430,6 +442,8 @@ inline CORINFO_InstructionSetFlags EnsureInstructionSetFlagsAreValid(CORINFO_Ins
             resultflags.RemoveInstructionSet(InstructionSet_Vector256);
         if (resultflags.HasInstructionSet(InstructionSet_AVXVNNI) && !resultflags.HasInstructionSet(InstructionSet_AVX2))
             resultflags.RemoveInstructionSet(InstructionSet_AVXVNNI);
+        if (resultflags.HasInstructionSet(InstructionSet_SHA) && !resultflags.HasInstructionSet(InstructionSet_SSE2))
+            resultflags.RemoveInstructionSet(InstructionSet_SHA);
 #endif // TARGET_X86
 
     } while (!oldflags.Equals(resultflags));
@@ -560,6 +574,10 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
             return "AVXVNNI";
         case InstructionSet_AVXVNNI_X64 :
             return "AVXVNNI_X64";
+        case InstructionSet_SHA :
+            return "SHA";
+        case InstructionSet_SHA_X64 :
+            return "SHA_X64";
 #endif // TARGET_AMD64
 #ifdef TARGET_X86
         case InstructionSet_X86Base :
@@ -600,6 +618,8 @@ inline const char *InstructionSetToString(CORINFO_InstructionSet instructionSet)
             return "Vector256";
         case InstructionSet_AVXVNNI :
             return "AVXVNNI";
+        case InstructionSet_SHA :
+            return "SHA";
 #endif // TARGET_X86
 
         default:
@@ -648,6 +668,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
         case READYTORUN_INSTRUCTION_Pclmulqdq: return InstructionSet_PCLMULQDQ;
         case READYTORUN_INSTRUCTION_Popcnt: return InstructionSet_POPCNT;
         case READYTORUN_INSTRUCTION_AvxVnni: return InstructionSet_AVXVNNI;
+        case READYTORUN_INSTRUCTION_Sha: return InstructionSet_SHA;
 #endif // TARGET_AMD64
 #ifdef TARGET_X86
         case READYTORUN_INSTRUCTION_X86Base: return InstructionSet_X86Base;
@@ -667,6 +688,7 @@ inline CORINFO_InstructionSet InstructionSetFromR2RInstructionSet(ReadyToRunInst
         case READYTORUN_INSTRUCTION_Pclmulqdq: return InstructionSet_PCLMULQDQ;
         case READYTORUN_INSTRUCTION_Popcnt: return InstructionSet_POPCNT;
         case READYTORUN_INSTRUCTION_AvxVnni: return InstructionSet_AVXVNNI;
+        case READYTORUN_INSTRUCTION_Sha: return InstructionSet_SHA;
 #endif // TARGET_X86
 
         default:

src/coreclr/inc/jiteeversionguid.h

@@ -43,11 +43,11 @@ typedef const GUID *LPCGUID;
 #define GUID_DEFINED
 #endif // !GUID_DEFINED
 
-constexpr GUID JITEEVersionIdentifier = { /* ccb0c159-04b3-47f6-993e-79114c9cbef8 */
-    0xccb0c159,
-    0x04b3,
-    0x47f6,
-    {0x99, 0x3e, 0x79, 0x11, 0x4c, 0x9c, 0xbe, 0xf8}
+constexpr GUID JITEEVersionIdentifier = { /* 5d34d51d-e6db-428c-a2f9-04e78ca09786 */
+    0x5d34d51d,
+    0xe6db,
+    0x428c,
+    {0xa2, 0xf9, 0x04, 0xe7, 0x8c, 0xa0, 0x97, 0x86}
   };
 
 //////////////////////////////////////////////////////////////////////////////////////////////////////////

src/coreclr/inc/readytoruninstructionset.h

@@ -34,6 +34,7 @@ enum ReadyToRunInstructionSet
     READYTORUN_INSTRUCTION_Dp=23,
     READYTORUN_INSTRUCTION_Rdm=24,
     READYTORUN_INSTRUCTION_AvxVnni=25,
+    READYTORUN_INSTRUCTION_Sha=26,
 
 };
 

src/coreclr/jit/emitxarch.cpp

@@ -54,6 +54,11 @@ bool emitter::IsBMIInstruction(instruction ins)
     return (ins >= INS_FIRST_BMI_INSTRUCTION) && (ins <= INS_LAST_BMI_INSTRUCTION);
 }
 
+bool emitter::IsSHAInstruction(instruction ins)
+{
+    return (ins >= INS_sha1msg1) && (ins <= INS_sha256rnds2);
+}
+
 regNumber emitter::getBmiRegNumber(instruction ins)
 {
     switch (ins)
@@ -576,7 +581,8 @@ static bool IsDstSrcImmAvxInstruction(instruction ins)
 // in use, since that encoding does not require an additional byte.
 bool emitter::Is4ByteSSEInstruction(instruction ins)
 {
-    return !UseVEXEncoding() && EncodedBySSE38orSSE3A(ins);
+    // `SHA` instructions do not support the VEC encoding and are always `SSE38` or `SSE3A`
+    return (!UseVEXEncoding() && EncodedBySSE38orSSE3A(ins)) || IsSHAInstruction(ins);
 }
 
 // Returns true if this instruction requires a VEX prefix
@@ -585,6 +591,7 @@ bool emitter::TakesVexPrefix(instruction ins) const
 {
     // special case vzeroupper as it requires 2-byte VEX prefix
     // special case the fencing, movnti and the prefetch instructions as they never take a VEX prefix
+    // CRC32 and SHA instructions never take a VEX prefix
     switch (ins)
     {
         case INS_lfence:
@@ -596,6 +603,13 @@ bool emitter::TakesVexPrefix(instruction ins) const
         case INS_prefetcht2:
         case INS_sfence:
         case INS_vzeroupper:
+        case INS_crc32:
+        case INS_sha1msg1:
+        case INS_sha1msg2:
+        case INS_sha1nexte:
+        case INS_sha1rnds4:
+        case INS_sha256msg2:
+        case INS_sha256rnds2:
             return false;
         default:
             break;
@@ -10380,7 +10394,7 @@ BYTE* emitter::emitOutputAM(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
 
         dst += emitOutputRexOrVexPrefixIfNeeded(ins, dst, code);
 
-        if (UseVEXEncoding() && (ins != INS_crc32))
+        if (UseVEXEncoding() && TakesVexPrefix(ins))
         {
             // Emit last opcode byte
             // TODO-XArch-CQ: Right now support 4-byte opcode instructions only
@@ -11164,7 +11178,7 @@ BYTE* emitter::emitOutputSV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
 
         dst += emitOutputRexOrVexPrefixIfNeeded(ins, dst, code);
 
-        if (UseVEXEncoding() && (ins != INS_crc32))
+        if (UseVEXEncoding() && TakesVexPrefix(ins))
         {
             // Emit last opcode byte
             // TODO-XArch-CQ: Right now support 4-byte opcode instructions only
@@ -11632,7 +11646,7 @@ BYTE* emitter::emitOutputCV(BYTE* dst, instrDesc* id, code_t code, CnsVal* addc)
 
         dst += emitOutputRexOrVexPrefixIfNeeded(ins, dst, code);
 
-        if (UseVEXEncoding() && (ins != INS_crc32))
+        if (UseVEXEncoding() && TakesVexPrefix(ins))
         {
             // Emit last opcode byte
             // TODO-XArch-CQ: Right now support 4-byte opcode instructions only
@@ -16262,7 +16276,48 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
             result.insThroughput = PERFSCORE_THROUGHPUT_140C;
             break;
         }
-
+        case INS_sha1msg1:
+        {
+            result.insLatency    = PERFSCORE_LATENCY_2C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_1C;
+            break;
+        }
+        case INS_sha1msg2:
+        {
+            result.insLatency    = PERFSCORE_LATENCY_6C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_2C;
+            break;
+        }
+        case INS_sha1nexte:
+        {
+            result.insLatency    = PERFSCORE_LATENCY_3C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_1C;
+            break;
+        }
+        case INS_sha1rnds4:
+        {
+            result.insLatency    = PERFSCORE_LATENCY_7C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_1C;
+            break;
+        }
+        case INS_sha256msg1:
+        {
+            result.insLatency    = PERFSCORE_LATENCY_5C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_2C;
+            break;
+        }
+        case INS_sha256msg2:
+        {
+            result.insLatency    = PERFSCORE_LATENCY_6C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_4C;
+            break;
+        }
+        case INS_sha256rnds2:
+        {
+            result.insLatency    = PERFSCORE_LATENCY_8C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_1C;
+            break;
+        }
         default:
             // unhandled instruction insFmt combination
             perfScoreUnhandledInstruction(id, &result);

src/coreclr/jit/emitxarch.h

@@ -89,6 +89,7 @@ static bool IsAVXOnlyInstruction(instruction ins);
 static bool IsFMAInstruction(instruction ins);
 static bool IsAVXVNNIInstruction(instruction ins);
 static bool IsBMIInstruction(instruction ins);
+static bool IsSHAInstruction(instruction ins);
 
 static regNumber getBmiRegNumber(instruction ins);
 static regNumber getSseShiftRegNumber(instruction ins);

src/coreclr/jit/hwintrinsiccodegenxarch.cpp

@@ -258,7 +258,7 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
                         genHWIntrinsicJumpTableFallback(intrinsicId, op2Reg, baseReg, offsReg, emitSwCase);
                     }
                 }
-                else if (node->TypeGet() == TYP_VOID)
+                else if ((node->TypeGet() == TYP_VOID) || (isa == InstructionSet_SHA))
                 {
                     genHWIntrinsic_R_RM(node, ins, simdSize, op1Reg, op2);
                 }

src/coreclr/jit/hwintrinsiclistxarch.h

@@ -823,6 +823,19 @@ HARDWARE_INTRINSIC(SSE2,            UCOMISD,
 HARDWARE_INTRINSIC(SSE41,           PTEST,                                      16,              2,     {INS_ptest,             INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,             HW_Flag_NoRMWSemantics)
 HARDWARE_INTRINSIC(AVX,             PTEST,                                       0,              2,     {INS_ptest,             INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_ptest,              INS_vtestps,            INS_vtestpd},           HW_Category_SimpleSIMD,             HW_Flag_NoRMWSemantics)
 
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+//                 ISA              Function name                               SIMD size       NumArg                                                                                                         Instructions                                                                                                                             Category                            Flags
+//                                                                                                      {TYP_BYTE,              TYP_UBYTE,              TYP_SHORT,              TYP_USHORT,             TYP_INT,                TYP_UINT,               TYP_LONG,               TYP_ULONG,              TYP_FLOAT,              TYP_DOUBLE}
+// ***************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************************
+//  SHA Intrinsics
+HARDWARE_INTRINSIC(SHA,            Sha1MessageSchedule1,                           16,             2,      {INS_invalid,           INS_sha1msg1,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,            HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SHA,            Sha1MessageSchedule2,                           16,             2,      {INS_invalid,           INS_sha1msg2,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,            HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SHA,            Sha1NextE,                                      16,             2,      {INS_invalid,           INS_sha1nexte,           INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,            HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SHA,            Sha1FourRounds,                                 16,             3,      {INS_invalid,           INS_sha1rnds4,           INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,            HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SHA,            Sha256MessageSchedule1,                         16,             2,      {INS_invalid,           INS_sha256msg1,          INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,            HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SHA,            Sha256MessageSchedule2,                         16,             2,      {INS_invalid,           INS_sha256msg2,          INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,            HW_Flag_NoFlag)
+HARDWARE_INTRINSIC(SHA,            Sha256TwoRounds,                                16,             3,      {INS_invalid,           INS_sha256rnds2,         INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid,            INS_invalid},           HW_Category_SimpleSIMD,            HW_Flag_NoFlag)
+
 #endif // FEATURE_HW_INTRINSIC
 
 #undef HARDWARE_INTRINSIC