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Fix STLUR for 0 imm #106760

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Merged
EgorBo merged 2 commits into from
Aug 24, 2024
Merged

Fix STLUR for 0 imm #106760

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ebb3941
fix stlur for 0 imm
EgorBo Aug 22, 2024
ab3088c
address feedback
EgorBo Aug 23, 2024
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15 changes: 9 additions & 6 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -5614,8 +5614,6 @@ void emitter::emitIns_R_R_I(instruction ins,
isLdSt = true;
break;

case INS_ldapurb:
case INS_stlurb:
case INS_ldurb:
case INS_sturb:
// size is ignored
Expand All @@ -5633,9 +5631,7 @@ void emitter::emitIns_R_R_I(instruction ins,
break;

case INS_ldurh:
case INS_ldapurh:
case INS_sturh:
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@amanasifkhalid amanasifkhalid Aug 23, 2024

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While you're here, could you please move these cases up to INS_ldurb/INS_sturb since they have the same behavior?

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@EgorBo EgorBo Aug 23, 2024

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Addressed. They indeed have the same issue but we never use them 🙂

case INS_stlurh:
// size is ignored
unscaledOp = true;
scale = 0;
Expand All @@ -5661,10 +5657,17 @@ void emitter::emitIns_R_R_I(instruction ins,
isLdrStr = true;
break;

case INS_ldur:
case INS_stur:
case INS_ldapurb:
case INS_ldapurh:
case INS_ldapur:
case INS_stlurb:
case INS_stlurh:
case INS_stlur:
fmt = IF_LS_2C;
break;

case INS_ldur:
case INS_stur:
// Is the target a vector register?
if (isVectorRegister(reg1))
{
Expand Down