Test failure: JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r/AdvSimd_r.sh #33948
Description
test failed in job: runtime-coreclr gcstress-extra 20200321.1
Error message
cmdLine:/root/helix/work/workitem/JIT/HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r/AdvSimd_r.sh Timed Out
Return code: -100
Raw output file: /root/helix/work/workitem/JIT/HardwareIntrinsics/Reports/JIT.HardwareIntrinsics/Arm/AdvSimd/AdvSimd_r/AdvSimd_r.output.txt
Raw output:
BEGIN EXECUTION
/root/helix/work/correlation/corerun AdvSimd_r.dll ''
Supported ISAs:
AdvSimd: True
Aes: True
ArmBase: True
Crc32: True
Sha1: True
Sha256: True
Beginning test case Abs.Vector64.Int16 at 3/21/2020 11:21:34 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_Load
Beginning scenario: RunClsVarScenario
Beginning scenario: RunClsVarScenario_Load
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_Load
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassLclFldScenario_Load
Beginning scenario: RunClassFldScenario
Beginning scenario: RunClassFldScenario_Load
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructLclFldScenario_Load
Beginning scenario: RunStructFldScenario
Beginning scenario: RunStructFldScenario_Load
Ending test case at 3/21/2020 11:22:05 PM
Beginning test case Abs.Vector64.Int32 at 3/21/2020 11:22:05 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_Load
Beginning scenario: RunClsVarScenario
Beginning scenario: RunClsVarScenario_Load
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_Load
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassLclFldScenario_Load
Beginning scenario: RunClassFldScenario
Beginning scenario: RunClassFldScenario_Load
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructLclFldScenario_Load
Beginning scenario: RunStructFldScenario
Beginning scenario: RunStructFldScenario_Load
Ending test case at 3/21/2020 11:22:12 PM
Beginning test case Abs.Vector64.SByte at 3/21/2020 11:22:12 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_Load
Beginning scenario: RunClsVarScenario
Beginning scenario: RunClsVarScenario_Load
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_Load
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassLclFldScenario_Load
Beginning scenario: RunClassFldScenario
Beginning scenario: RunClassFldScenario_Load
Beginning scenario: RunStructLclFldScenario
Beginning scenario: RunStructLclFldScenario_Load
Beginning scenario: RunStructFldScenario
Beginning scenario: RunStructFldScenario_Load
Ending test case at 3/21/2020 11:22:19 PM
Beginning test case Abs.Vector64.Single at 3/21/2020 11:22:19 PM
Random seed: 20010415; set environment variable CORECLR_SEED to this value to repro
Beginning scenario: RunBasicScenario_UnsafeRead
Beginning scenario: RunBasicScenario_Load
Beginning scenario: RunReflectionScenario_UnsafeRead
Beginning scenario: RunReflectionScenario_Load
Beginning scenario: RunClsVarScenario
Beginning scenario: RunClsVarScenario_Load
Beginning scenario: RunLclVarScenario_UnsafeRead
Beginning scenario: RunLclVarScenario_Load
Beginning scenario: RunClassLclFldScenario
Beginning scenario: RunClassLclFldScenario_Load
Beginning scenario: RunClassFldScenario
Beginning scenario: RunClassFldScenario_Load
Begin
Stack trace
at JIT_HardwareIntrinsics._Arm_AdvSimd_AdvSimd_r_AdvSimd_r_._Arm_AdvSimd_AdvSimd_r_AdvSimd_r_sh() in /__w/1/s/artifacts/tests/coreclr/Linux.arm64.Checked/TestWrappers/JIT.HardwareIntrinsics/JIT.HardwareIntrinsics.XUnitWrapper.cs:line 334
category:correctness
theme:testing
skill-level:expert
cost:medium