Describe the bug
node.send_output() causes SIGBUS (signal 7) on aarch64 platforms with strict NEON alignment requirements (e.g. NVIDIA Jetson NX / Carmel core) when the payload is ≥ 4 KB. The same code works correctly on x86 and on some other aarch64 platforms (e.g. Orange Pi / Cortex-A76).
Root cause: in zenoh_publish (apis/rust/node/src/node/mod.rs), when the payload exceeds ZERO_COPY_THRESHOLD (4096 bytes), the data is transferred via Zenoh shared memory (SHM). The SHM sub-allocation is requested with size only:
provider.alloc(data.len())
.with_policy::<BlockOn>()
.wait()
Zenoh's Talc sub-allocator returns a pointer at arbitrary alignment within the mmap-backed SHM region. On the receiving side (event_stream/mod.rs), this pointer is wrapped zero-copy as an Arrow Buffer via Buffer::from_custom_allocation. Because copy_array_into_sample only guarantees relative offset alignment between Arrow buffers (not the absolute address of the SHM base), if the base pointer is not 64-byte aligned, all Arrow buffer absolute addresses (shm_base + relative_offset) violate Arrow's SIMD alignment requirement (64 bytes).
On x86, unaligned SIMD access is handled silently in hardware. On Cortex-A76/A55 (Orange Pi), the core degrades unaligned NEON access to multiple aligned accesses. On NVIDIA Carmel (Jetson NX) running the L4T kernel, unaligned NEON access raises SIGBUS immediately with no fallback.
Describe the bug
node.send_output() causes SIGBUS (signal 7) on aarch64 platforms with strict NEON alignment requirements (e.g. NVIDIA Jetson NX / Carmel core) when the payload is ≥ 4 KB. The same code works correctly on x86 and on some other aarch64 platforms (e.g. Orange Pi / Cortex-A76).
Root cause: in zenoh_publish (apis/rust/node/src/node/mod.rs), when the payload exceeds ZERO_COPY_THRESHOLD (4096 bytes), the data is transferred via Zenoh shared memory (SHM). The SHM sub-allocation is requested with size only:
provider.alloc(data.len())
.with_policy::<BlockOn>()
.wait()
Zenoh's Talc sub-allocator returns a pointer at arbitrary alignment within the mmap-backed SHM region. On the receiving side (event_stream/mod.rs), this pointer is wrapped zero-copy as an Arrow Buffer via Buffer::from_custom_allocation. Because copy_array_into_sample only guarantees relative offset alignment between Arrow buffers (not the absolute address of the SHM base), if the base pointer is not 64-byte aligned, all Arrow buffer absolute addresses (shm_base + relative_offset) violate Arrow's SIMD alignment requirement (64 bytes).
On x86, unaligned SIMD access is handled silently in hardware. On Cortex-A76/A55 (Orange Pi), the core degrades unaligned NEON access to multiple aligned accesses. On NVIDIA Carmel (Jetson NX) running the L4T kernel, unaligned NEON access raises SIGBUS immediately with no fallback.