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Pull requests: diffblue/hw-cbmc

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Pull requests list

IC3: accept AG and G properties engines
#1969 opened Jul 4, 2026 by kroening Collaborator Loading…
Verilog: fix procedural assignment to imported package variables Verilog
#1968 opened Jul 2, 2026 by kroening Collaborator Loading…
2 tasks done
Verilog: support procedural assignment to hierarchical identifiers Verilog
#1967 opened Jul 2, 2026 by kroening Collaborator Loading…
3 tasks done
Support .f command files
#1961 opened Jul 2, 2026 by kroening Collaborator • Draft
4 tasks done
1
Verilog: parse fork...join_any and fork...join_none
#1950 opened Jun 28, 2026 by kroening Collaborator • Draft
1 task done
Verilog: handle deassign, release, and disable in convert_statement
#1949 opened Jun 28, 2026 by kroening Collaborator • Draft
1 task done
Verilog: support dynamic array declarators in merged_type
#1948 opened Jun 28, 2026 by kroening Collaborator • Draft
1 task done
Verilog: handle streaming concatenation with multiple stream expressions
#1947 opened Jun 28, 2026 by kroening Collaborator • Draft
1 task done
Verilog: skip method calls in convert_function_call_or_task_enable
#1946 opened Jun 28, 2026 by kroening Collaborator • Draft
1 task done
Verilog: add missing statement types to collect_symbols
#1945 opened Jun 28, 2026 by kroening Collaborator • Draft
1 task done
Add vlsim: Verilog simulator using the src/verilog front-end
#1942 opened Jun 28, 2026 by kroening Collaborator Loading…
AIGER: KNOWNBUG tests for front-end bugs found by fuzzing
#1935 opened Jun 27, 2026 by kroening Collaborator Loading…
1
AIGER output
#1928 opened Jun 21, 2026 by kroening Collaborator • Draft
fastppa: word-level delay, area, and power estimation tool
#1927 opened Jun 21, 2026 by kroening Collaborator Loading…
1
9
Verilog: split synthesis into behavioral and structural cleanup Verilog
#1926 opened Jun 21, 2026 by kroening Collaborator • Draft
Verilog: support for let expressions with ports
#1925 opened Jun 21, 2026 by kroening Collaborator • Draft
SystemVerilog: named sequence/property ports Verilog
#1923 opened Jun 21, 2026 by kroening Collaborator • Draft
Verilog: preresolving identifiers Verilog
#1921 opened Jun 20, 2026 by kroening Collaborator Loading…
introduce verilog_let_typet Verilog
#1919 opened Jun 20, 2026 by kroening Collaborator • Draft
Verilog: derive identifier from annotated scope cleanup Verilog
#1912 opened Jun 19, 2026 by kroening Collaborator • Draft
verilog_identifier_exprt now has structured scope stack Verilog
#1910 opened Jun 19, 2026 by kroening Collaborator • Draft
Verilog: SystemVerilog interfaces
#1907 opened Jun 18, 2026 by kroening Collaborator Loading…
9 tasks done
Verilog: fix unsigned/signed parameter without explicit range Verilog
#1902 opened Jun 16, 2026 by kroening Collaborator • Draft
Verilog: $root module does not need ports cleanup Verilog
#1875 opened Jun 4, 2026 by kroening Collaborator • Draft
module types now contain the symbol set Verilog
#1869 opened May 24, 2026 by kroening Collaborator • Draft
ProTip! Updated in the last three days: updated:>2026-07-02.